s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 86

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

15.4
15.5
84
erase suspended,
actively erasing,
programming in
erase suspend
programming,
If device is
DQ2: Toggle Bit II
Reading Toggle Bits DQ6/DQ2
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected
for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to
page 84
See the following for additional information:
DQ6: Toggle Bit I
on page
Refer to
the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically, the system would note and store the value
of the toggle bit after the first read. After the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
at an address within sectors not
at an address within sectors not
at an address within a sector
at an address within a sector
106, and
to compare outputs for DQ2 and DQ6.
Figure 15.2, “Toggle Bit Algorithm,” on page 83
selected for erasure,
selected for erasure,
selected for erasure,
selected for erasure,
and the system reads
at any address,
at any address,
on page 82,
Table 15.1, “DQ6 and DQ2 Indications,” on page
Table 15.1 DQ6 and DQ2 Indications
Figure 22.18, “Toggle Bit Timings (During Embedded Algorithm),”
S29WS128J/064J
D a t a
returns array data,
does not toggle,
then DQ6
toggles,
toggles,
toggles,
toggles,
Figure 15.2, “Toggle Bit Algorithm,” on page
S h e e t
Table 15.1, “DQ6 and DQ2 Indications,” on
for the following discussion. Whenever
from any sector not selected for erasure.
returns array data. The system can read
84.
is not applicable.
does not toggle.
does not toggle.
also toggles.
and DQ2
toggles.
S29WS-J_M0_A4 June 24, 2005
83, See