s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 110

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not
4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency
108
RESET#
SA, A6,
A1, A0
crossing a bank in the process of performing an erase or program.
at the boundary crossing.
WE#
Data
OE#
CE#
Address (hex)
RDY(1)
RDY(2)
V
V
AVD#
OE#,
CE#f
Data
ID
IH
CLK
(stays low)
(stays high)
3C
1 µs
C60
Figure 22.22 Sector/Sector Block Protect and Unprotect Timing Diagram
D60
Sector Protect/Unprotect
00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
60h
3D
C61
Address boundary occurs every 64 words, beginning at address
D61
3E
C62
Figure 22.23 Latency with Boundary Crossing
Valid*
t
60h
RACC
D62
C63
3F
S29WS128J/064J
t
RACC
latency
Sector Unprotect: 1.5 ms
Sector Protect: 150 µs
D a t a
C63
3F
latency
D63
C63
S h e e t
3F
t
RACC
C63
3F
Valid*
Verify
40h
t
RACC
D63
C64
40
D64
C65
41
S29WS-J_M0_A4 June 24, 2005
D65
C66
42
Status
D66
Valid*