s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 173

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

37 Bus Operating Modes
37.1
172
Asynchronous Mode
These CellularRAM products incorporate the industry-standard, asynchronous interface found on
other low-power SRAM or Pseudo SRAM offerings. This bus interface supports asynchronous READ
and WRITE operations as well as the bandwidth-enhancing page mode READ operation. The spe-
cific interface that is supported is defined by the value loaded into the CR.
CellularRAM products power up in the asynchronous operating mode. This mode uses the indus-
try-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ operations
are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data is
driven out of the I/Os after the specified access time has elapsed. WRITE operations
occur when CE#, WE#, and LB#/UB# are driven LOW. During WRITE operations, the level of OE#
is a “Don't Care”; WE# overrides OE#. The data to be written is latched on the rising edge of CE#,
WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited to t
ADDRESS
Figure 37.2 Asynchronous Mode WRITE Operation
ADDRESS
LB#/UB#
Figure 37.1 Asynchronous Mode READ Operation
LB#/UB#
DATA
DATA
WE#
WE#
OE#
OE#
CE#
CE#
Aysnc/Page CellularRAM Type 2
A d v a n c e
t
WC = WRITE Cycle Time
t
RC = READ Cycle Time
I n f o r m a t i o n
ADDRESS VALID
ADDRESS VALID
<
t
CEM
DATA VALID
DATA VALID
DON’T CARE
DON’T CARE
CellRAM_05_A0 August 25, 2005
CEM
(Figure
(Figure
.
37.1)
37.2)