cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 236

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

8.0 DMA Coprocessor
8.7 Little Endian Mode
Figure 8-8. Master Data Byte Swap—32-bit Transfer
8-10
ATM Cell
Assumes PCI Address
8.7 Little Endian Mode
When no Endian bits are set, the SAR comes up in little Endian mode. The
following section describes transfers as seen in the PCI bus when the SAR is set
in default mode.
NOTE:
Space is Big Endian
0
Address[2:0] = 0
Address[2:0] = 1
12 13 14 15
15
11 12 13
0
4
8
3
7
Host Buffer
Host Buffer
1
MSTR_DWORD_SWAP must be set to 1.
0
1
5
9 10 11
4
8
2
Mindspeed Technologies
1
2
6
5
9
3
14
10
2
3
7
6
4
12
12
16
5
0
4
8
0
4
8
6
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
7
8
PCI Host Address Space Length
9 10 11 12 13 14 15
(Number of 32-bit words) = 4
Address[2:0] = 2
Address[2:0] = 3
10 11
14
12
6
0
4
8
2
Host Buffer
Host Buffer
™
15
15 14 13
11 10 9
7
3 2
7 6
3
12 13
0
4 5
8 9
1
5
1
12
16
12
16
0
4
8
0
4
8
28237-DSH-001-C
CN8237
8237_143