cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 325

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Table 14-4. PCI Configuration Field Descriptions (2 of 2)
28237-DSH-001-C
INTERRUPT_LINE
SPECIAL_STATUS
_REGISTER
MASTER_READ
_ADDR
MASTER_WRITE
_ADDR
EEPROM_REGISTER
PM_CAPABILITY
NEXT_CAP_PTR
CAPABILITY_ID
PM_DATA
PMCSR
HS_CSR
Field
Interrupt line identifier. The value in this register tells which input of the system interrupt controller(s)
the device’s interrupt pin is connected to. The device itself does not use this value; rather, it is used by
device drivers and operating systems.
Device status not defined by the PCI specification. The field is further subdivided into subfields as
shown in
The configuration registers are accessed starting from byte address 0 in the configuration space
allotted to an adapter card containing the SAR chip. Access to the configuration registers is available
only to the PCI host CPU, and is independent of all other SAR logic.
Current read target address used by PCI bus master (read only).
Current write target address used by PCI bus master (read only).
A 32-bit register controlling access to the Serial EEPROM. See
specific fields in the EEPROM_REGISTER.
Power Management Capabilities register. A 16-bit read-only register which provides information on the
capabilities of the function related to Power Management. See PCI Bus Power Management Interface
Specification, Revision 1.0 for specific information related to this register.
Next Item Pointer register. This field provides an offset into the PCI Configuration space pointing to the
location of the next item of the linked capability list. If there are no additional items in the Capabilities
List, this register is set to 0x58.
Capability Identifier. When set to 0x01, indicates that the linked list item being pointed to is the PCI
Power Management registers. Default value is 0x01.
Power Management Data register. This 8-bit read-only register provides a mechanism for the Power
Management function to report state-dependent operating data, such as power consumed or heat
dissipation. See PCI Bus Power Management Interface Specification, Revision 1.0 for specific
information related to this register.
Power Management Control/Status register. This 16-bit register is used to manage the PCI function’s
power management state, as well as to enable and monitor power management events. See PCI Bus
Power Management Interface Specification, Revision 1.0 for specific information related to this
register.
CompactPCI Hot Swap Control/Status register.
Table
14-7. Detailed descriptions of these subfields can be found in the PCI bus specification.
Mindspeed Technologies
Description
™
Table 14-8
14.7 PCI Bus Interface Registers
for a description of the
14.0 CN8237 Registers
14-35