cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 298

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

14.0 CN8237 Registers
14.2 System Registers
0x30
14-8
31–30
28–27
20–18
17–13
12–9
8–4
Bit
29
26
25
24
23
22
21
3
2
1
0
—
Configuration Register 1 (CONFIG1)
Field
Size
2
1
2
1
1
1
1
1
1
3
5
4
5
1
1
1
1
Reserved
PHY_STROBE_I0
PHY_WAIT
PHY_RST
Reserved
FR_LOOP
UTOPIA_MODE
MULTI_PHY
UTOP16
NUM_PORTS[2:0]
SLAVE_ADDR[4:0]
TAG_SIZE[3:0]
PHYBANK[4:0]
Reserved
TX_FIFO_FLUSH_EN
INCFIFO_SZ
NEW_PMOAM
Name
This register provides system control and configuration bits that are not directly
associated with the reassembly and segmentation coprocessors. The majority of
these configuration bits are set at initialization time and are not changed
dynamically. The assertion of the HRST* system reset pin clears all bits in the
CONFIG1 register except for UTOPIA_MODE, UTOPIA 16, and PHY_RST bit
which will be set.
Mindspeed Technologies
Set to 0.
Set to logic low for operation with Mindspeed framers.
Set to logic low for operation with Mindspeed framers.
When logic high, sets PRST* to logic low. Set to logic 1 upon reset.
Always set to 0.
When set, this bit enables loopback of cells at the ATM physical interface.
Selects octet or cell UTOPIA handshake mode. Set to logic 1 upon reset.
If logic high, multi-PHY operation is enabled.
If logic high, UTOPIA 16 bit interface is enabled; otherwise 8-bit interface.
Set to logic 1 upon reset.
Number of PHY ports to poll when in Master UTOPIA Mode starting with
address 0. Number of ports = (NUM_PORTS + 1)
When in Slave UTOPIA Multi-PHY Mode, this is the UTOPIA device address
of the SAR. When in Master Non-Multi-PHY Mode, this is the address
present on both TxADDR and RxADDR.
Select Tag size. When UTOP16 is logic high, valid range is 0 to 10 in even
increments. When UTOP16 is a logic low, valid range is 0 to 11.
Physical Chip Bank Select. This value is placed on PADDR[12:8] when a
PHY control access occurs.
Always set to 0.
Enables Tx FIFO flush mechanism. This mechanism is only valid in UTOPIA
master and multiphy mode.
Incoming DMA FIFO buffer size. Logic high sets the FIFO buffer to 8 KB,
logic low to 2 KB.
When a logic high, the new PM_OAM mechanism is enabled per ITU-T
Recommendation I.610, June 98.
0 = Octet
1 = Cell handshake
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
Description
28237-DSH-001-C
CN8237