cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 28

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

1.0 CN8237 Product Overview
1.1 Introduction
1-2
separate control and status queues. Each VCC in a peer group can be limited to a
specific maximum receive buffer utilization, further controlling congestion. EPD
is supported for VCCs exceeding their resource allotments. On transmit, peers are
assigned fixed or round-robin priority to ensure predictable servicing. The host
implements a congestion notification algorithm for ABR with a simple one-word
write to a SAR control register. The SAR either reduces the Explicit Rate (ER)
field or sets the Congestion Indication (CI) bit in Turnaround Resource
Management (RM) cells, based on user configuration.
SAR-controlled through local bus interfaces and arbitrates access to the busses
between the users. The coprocessors run off the same system clock but operate
asynchronously from each other. Communication between the coprocessors takes
place through on-chip FIFO buffers or through queues in SAR-shared memory
(that is, memory local to the SAR and accessible to both the SAR and the host).
and UTOPIA ports that provide glueless interfaces to a variety of systems. The
interfaces have full line rate throughput and low bus occupancy.
Each coprocessor maintains state information in local memory. This memory is
The host interface controls host congestion by having each peer maintain
The CN8237 consists of five separate coprocessors:
• Incoming DMA
• Outgoing DMA
• Reassembly
• Segmentation
• xBR Traffic Manager
The CN8237 on-chip coprocessors are surrounded by high performance PCI
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237