FM24C256FEYYX FAIRCHILD [Fairchild Semiconductor], FM24C256FEYYX Datasheet - Page 5

no-image

FM24C256FEYYX

Manufacturer Part Number
FM24C256FEYYX
Description
256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
FM24C256 rev. B.3
FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
(Note 2)
t
t
t
t
t
HD:DAT
SU:STO
HD:STA
SU:STA
SU:DAT
t
: The write cycle time (t
t
f
t
HIGH
t
LOW
t
SCL
t
BUF
T
t
WR
AA
t
DH
R
F
I
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
V
10 ns
V
1 TTL Gate and C
CC
CC
x 0.1 to V
x 0.5
IN
CC
x 0.9
L
= 100 pF
250
100
0.3
4.7
4.0
4.7
4.7
4.0
4.7
0
100
100
300
3.5
1
6
100
100
0.3
1.3
0.6
1.5
0.6
0.6
0.6
0
400
300
1.2
0.3
50
6
www.fairchildsemi.com
kHz
ms
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns

Related parts for FM24C256FEYYX