cxa3516r Sony Electronics, cxa3516r Datasheet - Page 50

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

• 1/2 clock output
• Delay sync output
1/2 clock signal is a signal that resets the clock by using a reset pulse created from an internal delay sync
signal and divides the clock in half. The complementary signal is output from the 1/2CLK (Pin 101) and
1/2XCLK (Pin 100). (See the PLL timing diagram). Although the 1/2 clock output can also be independently
turned off by the control register, it cannot be set to high impedance.
Two types of delay sync signal (DSYNC and DIVOUT) can be output from the DSYNC/DIVOUT (Pin 103).
This is selected by switching a control register. The DSYNC signal is output as the input SYNC signal
undergone timing control. The DIVOUT signal is output as the programmable counter output undergone
timing control.
Both can be used as reset signals for any connected IC such as a scaling IC.
Delay sync output signal (DSYNC/DIVOUT (Pin 103))
Signal output from the DSYNC/DIVOUT pin
• DSYNC signal
• DIVOUT signal
[Function Correspondence Table for the DSYNC Signal/DIVOUT Signal]
Register: 1/2CLK Enable, 1/2XCLK Enable
A SYNC signal input that has been timing controlled by a clock generated by a PLL is output.
Although only the forward edge is completely managed at this time with delay settings, etc., the back
edge has an undefined width for one clock cycle because it latches and outputs the input SYNC signal.
A timing controlled programmable counter output signal is output. In addition to the COARSE DELAY
that has been set by using the DSYNC signal, the delay time setting is output with a delay of 4 or 5
clocks. The pulse width is also managed by a clock.
Output during HOLD
COARSE DELAY
DIVOUT DELAY
Output polarity
Output enable
FINE DELAY
Pulse width
Function
Register: DSYNC By-pass
1/2 Clock Output Status
Fixed (depends on input
SYNC signal width)
1/32CLK to 64/32CLK
DSYNC signal
3CLK to 6CLK
On/Off
On/Off
On/Off
—
DIVOUT signal
– 50 –
0
Off
0
1/32CLK to 64/32CLK
DIVOUT signal
3CLK to 6CLK
1, 2, 4, 8CLK
DSYNC signal
4, 5CLK
On/Off
On/Off
On/Off
1
On
1
COARSE DELAY
DIVOUT WIDTH
DIVOUT DELAY
DSYNC Enable
FINE DELAY
DSYNC Hold
DSYNC POL
Register
CXA3516R