cxa3516r Sony Electronics, cxa3516r Datasheet - Page 58

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

• UNLOCK timing
If the phase difference between the SYNC signal input and the programmable counter output signal to the
phase detector (PD) increases, it becomes impossible for the VCO to maintain stable oscillation. This status is
converted into the UNLOCK signal and output. It is possible to perform analog lock/unlock by connecting an
external circuit to this pin.
The UNLOCK output is an open collector. By connecting the external circuit shown above to this output pin, it
is possible to adjust the sensitivity of the S2 signal by varying the constants R1, R2 and C1. (The constants
R1, R2 and C1 above are reference values. The resistor R3 should be 50k and Q1 should be 2SC series.
The operations of the three cases are described below.
Case 1: When there is no phase difference (PLL locked status)
Case 2: When there is a phase difference, the S1 signal will goes low and high as shown in the figure below.
Case 3: However, even if the same phase difference as described above is assumed, the decreasing resistor
The S1 signal is low and the S2 signal is high. The UNLOCK signal is low.
At this time, the falling edge slew rate of the S2 signal is determined by the current I1 flowing into this
open collector. The falling edge slew rate of the S2 signal will therefore be delayed as resistor R1
increases. In addition, since the rising edge slew rate of the S2 signal is determined by the current I2,
the rising edge slew rate of the S2 signal will become faster as the resistor R2 decreases. If the
integrated S2 signal does not fall below the threshold level of the next inverter, the UNLOCK signal
will remain low. This will therefore be judged as locked even if there is a phase difference.
R1 will increase the current I1 flowing into the open collector. The falling edge slew rate of the S2
signal will therefore become faster. In addition, if resistor R2 is increased, the rising edge slew rate of
the S2 signal will become slower. If the integrated S2 signal is under the threshold level of the next
inverter, the UNLOCK signal will go from low to high and the PLL will be judged as unlocked.
UNLOCK signal
UNLOCK signal
UNLOCK signal
S1 signal
S2 signal
S1 signal
S2 signal
S1 signal
S2 signal
Signal from the
phase detector
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
UNLOCK
detect
IC internal
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104
S1 signal
Vcc
R3
50k
IC external
Q1
R1
R1 = 100
R2 = 100k
C1 = 0.01 F
I1
I2
Vcc
S2 signal
R2
C1
UNLOCK signal
Threshold level
of the inverter
Threshold level
of the inverter
Threshold level
of the inverter
CXA3516R