cxa3516r Sony Electronics, cxa3516r Datasheet - Page 56

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

Notes on Using the HOLD Signal and XTLOAD Signal (Reset Signal)
If the cycle of the SYNC signal is lost, the phase difference between the SYNC signal and the programmable
counter output in the phase detector will increase, and it will cause PLL unlock. At this time, the HOLD signal is
input to the HOLD (Pin 106), phase comparison is stopped while the signal is high level (when the HOLD POL
register is set to "1"), and the clock can be stably oscillated by holding the VCO oscillation frequency. Note,
however, the correspondence differs depending on whether the number of locations where the SYNC signal
period changes (the 0.5H region in the diagram) is odd or even.
Case 1: When the 0.5H region is even (correspondence with HOLD signal only)
When the number of the 0.5H period is even, it is possible to hold the period of the programmable counter
output stable by applying the HOLD signal before the frequency changes.
This corresponds to the vertical blanking period of the composite sync (computer signal).
Case 2: When the 0.5H region is odd (correspondence with HOLD signal + XTLOAD signal (reset signal))
When the number of the 0.5H period is odd, if only the HOLD signal is used, the phase difference between the
SYNC signal and the programmable counter output signal will increase in the extra 0.5H region and the lock
will be lost momentarily.
In this case, the 0.5H region is held by the HOLD signal, and it is possible to use the XTLOAD signal (reset
signal) at 1H backward to the official counter period by resetting/setting the counter value.
Although there are no particular restrictions on the setup time and hold time of the XTLOAD signal (reset
signal), the pulse width of the XTLOAD signal (reset signal) is restricted while the HOLD signal is high. (When
the HOLD POL register is set to "1".)
If the rising edge of the XTLOAD signal (reset signal) is delayed by 8CLK from the falling edge of the SYNC
signal, counter output will be obtained by synchronizing with the falling edge of the next SYNC signal. See the
diagram for details on timing.
Programmable
counter output signal
Programmable
counter output signal
(SYNC POL = 0)
(SYNC POL = 0)
XTLOAD signal
SYNC signal
HOLD signal
(reset signal)
SYNC signal
HOLD signal
SYNC signal
H
H
0.5H 0.5H 0.5H
PD
1
H
2
Tw (min) = 100ns
0.5H 0.5H 0.5H 0.5H
1
– 56 –
3
LPF
CP
Programmable
counter
2
H
8CLK
3
VCO
4
"HSYNC" and "XTLOAD" are synchronized
H
DIV
1, 2, 4, 8
H
H
H
Clock output
H
CXA3516R