cxa3516r Sony Electronics, cxa3516r Datasheet - Page 69

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

The hold time of the post-stage scaling IC using the interface shown above is,
(4:2:2 Data out D2 Mode)
The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC.
The analog signal input to the ADC is sampled by using a clock generated by the PLL.
The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99).
In 4:2:2 Data out D2 Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to
the data output ports GA0 to GA7. The Cb and Cr signals are all simultaneously A/D converted at a half
sampling rate compared with the Y signal, then multiplexed within the IC, and output to the data output ports
BA0 to BA7 in the order U (Cb) and V (Cr).
When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the
signal. See the operational description of SYNCSEP for details.
Data output of ADC possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus
the clock output from the CLK pin.
The operating frequency in 4:2:2 Data out D2 Mode is 100MHz as the sampling clock frequency.
Although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the
IC operates in 4:2:2 Data out D2 Mode, they cannot be set to high impedance.
All TTL output is set to high impedance when this IC is put into power save mode.
An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode.
th (min.) = 2.2ns
CXA3516R
GA0 to GA7
BA0 to BA7
1/2XCLK
1/2CLK
XCLK
CLK
99
98
101
100
max.
min.
– 69 –
Td_8
2.2ns (min.) to 3.8ns (max.)
Scaling IC
CXA3516R