cxa3516r Sony Electronics, cxa3516r Datasheet - Page 57

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

DIVOUT signal
(when DSYNC POL = 0)
• HOLD signal timing
SYNC signal
(when SYNC POL = 1)
SYNC signal
(when SYNC POL = 0)
HOLD signal
(when HOLD POL = 1)
The HOLD signal setup time (Ths) is the time from the rising edge of the HOLD signal to the falling edge of
the DIVOUT signal. The HOLD signal hold time (Thh) is the time from the falling edge of the DIVOUT signal
to the rising edge of the HOLD signal. See the above timing diagram for details on the relationship with
SYNC POL.
The frequency variation of CLK while held can be calculated as given below.
C · V = Q = I
For example,
V = Ileak · Thold/C
f = V · KVCO = I
C: Loop filter capacitance
I
Thold: Hold time
Assuming f = 100MHz, I
leak
V: Varying voltage due to leak current
V = 1 · 10
f = 1 · 10
: Leak current of the internal amplifier
Clock output
SW
SW
I
I
–9
leak
–9
· 1 · 10
· 1 · 10
· Thold
leak
· Thold/C · KVCO
–3
VCO oscillation frequency is held without performing phase comparison.
–3
/(0.1 · 10
I
/(0.1 · 10
leak
leak
+Q
= 1nA, Thold = 1ms, C = 0.33µF, KVCO = 2 · 55 [MHz/V],
C
–6
–6
V
) · 2 · 70 · 10
–Q
) = 3 · 10
–6
[V]
Thh
6
= 1050 [Hz]
– 57 –
Ths
VCO
Thold
f
Thh
Ths
CXA3516R