cxa3516r Sony Electronics, cxa3516r Datasheet - Page 68

• Manufacturer Part Number: cxa3516r
• Description: 3-channel 8-bit 165msps A/d Converter Amplifier Pll
• Manufacturer: Sony Electronics

With the interface shown above, port A data is acquired into the post-stage scaling IC by using the clock
signal output from the 1/2CLK pin of the ADC, while port B data is acquired by using the clock signal output
from the 1/2XCLK pin.
In case of this interface, the setup time of the post-stage scaling IC is,
While the hold time is,
(DMUX Interleaved Data out Mode)
The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC.
The analog signal input to the ADC is sampled by using a clock generated by the PLL.
The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each
clock cycle, sampled data is divided into pins in port A and port B.
The data output on the port A side possesses a 2-clock pipeline delay versus the sampling clock, while the
data output on the port B side also possesses a 2-clock pipeline delay.
Although the data output from both ports is maintained for two cycles (2T) of the sampling clock, there is one
cycle (T) difference between the output timing for port A side and port B side.
Data output on port A side possesses a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.)
versus the clock output from the 1/2XCLK (Pin 100), while data output on port B side possesses a
propagation delay (Td_1/2clk to data) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from
the 1/2CLK (Pin 101).
An interface of the following type is possible when this IC is run in DMUX Interleaved Data out Mode.
ts (min.) = T – 2.2ns
th (min.) = T + 1.3ns
CXA3516R
RA0 to RA7
GA0 to GA7
BA0 to BA7
RB0 to RB7
GB0 to GB7
BB0 to BB7
1/2XCLK
1/2CLK
XCLK
CLK
99
98
101
100
max.
min.
Td
max.
Td
min.
ts
– 68 –
Td_7
1.3ns (min.) to 2.2ns (max.)
Td
th
ts
T
th
Scaling IC
CXA3516R