CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 10

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

B2, CA1
B1, CA0
Data Registers
Address/Control: 0000000 to 0000111 - $00 to $0F
Read/Write: Read Only
The Data Registers are used to store the results of A/D con-
versions. There are two registers, a High Data Register and
a Low Data Register, associated with each channel.
In 8-bit mode, the High Data Registers are inaccessible, and
each Low Data Register holds the 8-bit result of the most
recent conversion of its associated channel. The values
range from $00 (AIn = V
During multiple byte Data Register reads, the address (held
in the CAR) is advanced to the Low Data Register of the next
active channel (as specified in the CSR) following each read.
In 10-bit mode, bits 0 and 1 of the High Data Register
together with the contents of the Low Data Register hold the
result of the most recent conversion to the associated
channel. The values range from $000 (AIn = V
scale reading of $3FF. During multiple byte Data Register
reads, the address (held in the CAR) is automatically
advanced from the High Data Register to the Low Data
Register. Following a read of the Low Data Register, the
address advances to the High Data Register of the next
active channel (as specified in the CSR).
Two status flags are maintained for each channel. In 10-bit
mode these status flags are provided in the High Data
Register. In 8-bit mode they are not available to the user.
Their functions are:
B7, DV
B6, DOV
High
H/L = 0
Low
H/L = 1
Channel Address, bit 1. See discussion under
CA2.
Channel Address, bit 0. See discussion under
CA2.
The Data Valid bit indicates whether the corre-
sponding channel has been converted since it
was last read. DV is set upon completion of a
conversion on the corresponding channel. DV is
cleared by reading the Data Register or by a
write to the MSR or the CSR.
NOTE: A write to the SAR does not clear the DV flag
for each channel. This implies that if: conversion are
completed on all registers selected in CSR; conver-
sions stopped; an incomplete read of the Data Regis-
ters is performed; and conversions reinitiated with a
write to the SAR - some DVs will still be set. In Mode
2, which terminates when all DVs are true (ACC goes
true), unread channels may not be converted, unless
CSR is written to, before setting ENC.
The Data Overrun (DOV) bit indicates that more
than one conversion has been performed on a
channel since it was last read. This bit is only
valid in Modes 1 and 3. DOV is cleared by read-
ing the Data Register or by performing a write to
the CSR or the MSR.
DV
D7
7
7
DOV
D6
6
6
SS
D5
0
5
5
) to a full scale reading of $FF.
D4
0
4
4
D3
0
3
3
D2
0
2
2
SS
D9
D1
1
1
) to a full
CDP68HC68A2
D8
D0
0
0
10
Conversion Modes of the CDP68HC68A2
Mode 0 - Idle
On power_up, the MSR is reset to all 0’s placing the A2 into
Mode 0. After power_up, the user can effectively reset the
A2 by selecting Mode 0 via the MSR. Setting the A2 to Mode
0, at any time, will abort any current conversions and force
the INT pin to a high impedance state. In mode 0, if EXT is
high in the MSR, the one pin, internal oscillator is placed in a
low power, shutdown mode and internal clocking of the A/D
converter is inhibited. If EXT is low in the MSR, internal
clocking of the A/D converter is inhibited.
Mode 1 - Single Conversion
In Mode 1, conversions are performed on command. After set-
ting Mode 1 in the MSR, a write to the SAR with ENC high will
initiate a conversion on the channel currently selected by the
CAR. Note: this channel does not have to be active in the CSR.
When using the internal oscillator, the oscillator is enabled. The
CIP flag in the SR will be set when the conversion begins.
Upon completion of the conversion, the INT bit in the SR will
be set, the CIP flag will cleared, and, if IE is true in the MSR,
the INT pin will be driven low (if all channels specified in the
CSR have been converted since the last Data Register read
the ACC bit in the SR will also be set). Finally, if it’s active,
the internal oscillator will be stopped.
Another conversion can be initiated with a write to the SAR.
However, the normal procedure is to read the results of the
first conversion. This does two things: first it clears the INT
flag (the INT pin is returned to a high impedance state);
second a conversion is automatically started on the next
channel selected in the CSR. This read-convert pattern can
be continued indefinitely.
When reading Data Registers in Mode 1, the user can be
certain that the contents of the CAR equal the channel num-
ber which was just converted. Thus the Address/Control
Byte sent prior to the read will automatically match the CAR.
If a read from a Data Register, other than the one just con-
verted, is performed, the CAR must be set to the desired
register prior to sending the Address/Control Byte. Setting
CAR is done by writing the SAR with ENC = 0, SAE = 1, and
the CA2 - CA0 bits equal to the desired channel.
Mode 2 - Single Scan
In mode 2, when ENC is set in the SAR, conversions are per-
formed on all channels selected in the CSR. Conversions
begin on the channel specified by the CAR (this channel does
not have to be active in the CSR) and proceed in ascending
order until all channels selected in the CSR have been con-
verted. If the starting channel is not the lowest active channel,
when the highest active channel is done converting, the CAR
advances to the lowest active channel and continues from that
point until all channels have been converted once.
When ENC is set i n the SAR, the internal clock is activated
(if selected), the CIP flag is set in the SR, and conversions
begin. The CIP flag doesn’t remain high, as it momentarily
goes low between each channel conversion.