CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 9

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

the number of a channel which is not selected in the CSR.
After the specified channel is converted, subsequent
conversions proceed in ascending order, skipping channels
not selected in the CSR. Therefore, jamming the CAR with a
non-selected channel number will cause a conversion to be
performed on that channel once and only once.
After stopping a Mode 2 or 3 conversion (by setting ENC
low), the CAR must be jammed to match the channel
address prior to initiating Data Register reads. If an
Address/Control Byte is sent to begin reads from a Data
Register other than the one currently addressed by the CAR,
the contents of the Data Register may be corrupted. If the
CAR contents are known, single or multiple byte reads can
be properly made, by sending a matching Address/Control
Byte.
Bits 5 and 6 in the SAR are “don’t cares” and can be set to
either 0’s or 1’s. The functions of the remaining bits are as
follows:
B7, ENC
B4, SAE
B3, CA2
B2, CA1
B1, CA0
B0, H/L
The Enable Conversions (ENC) bit is used to
synchronously switch on and off the successive
approximation A/D converter. When this bit is
set high, the appropriate conversion operation
(as defined in the MSR) is initiated. Setting the
ENC bit low stops the conversion operation. If a
channel is being converted when ENC is
cleared, the conversion of that channel will com-
plete and further conversions will be inhibited.
Starting Address Enable (SAE). If the SAR is
written to, with the SAE bit high, the CAR is
jammed with the value defined by CA2, CA1,
and CA0. If SAE is low, the CA2, CA1, and CA0
bits are ignored.
Channel Address, bit 2. When writing to the
SAR with SAE high, CA2, CA1, and CA0 form a
3-bit channel address which is used to set the
CAR and select the first channel to be converted
or read. Reading the SAR returns the previously
written values for these three bits. To determine
the contents of the CAR a read of the Status
Register (SR) must be performed.
Channel Address, bit 1. See discussion under
CA2.
Channel Address, bit 0. See discussion under
CA2.
High/Low. For most applications, the SAR
should be written with H/L as a 0. In combination
with CA2, CA21, and CA0, this bit is used to
select a specific High or Low Data Register. H/L
only has significance in 10-bit mode. The 10-bit
read sequence is High Data Register followed
by Low Data Register for each channel read.
When jamming the CAR prior to reads, H/L
should be set low, unless the user specifically
wants to skip the first High Data Register. When
read, this bit, indicates whether the next Data
Register read will access the High or Low Data
Register. In 8-bit mode, H/L is ignored by the A2.
CDP68HC68A2
9
Status Register (SR)
Address/Control: 00010011 - $13
Read/Write: Read Only
This is a read only register used to monitor the status of the
A/D converter. If an Address/Control Byte of $13 is sent to
the A2, the Status Register will be addressed and will remain
addressed until the CE pin is brought low. This provides effi-
cient polling of the SR by allowing multiple reads of the SR
with only one Address/Control Byte transmission.
Bits 0 and 4 of the SR are always read as lows. The
significance of each of the other bits is:
B7, INT
B6, ACC
B5, CIP
B3, CA2
INT
7
ACC
6
Interrupt. In Modes 1 and 2, this bit is set high
under the same conditions that the INT pin
would be activated (see Conversion Modes).
Once set, the INT bit can be cleared by reading
the SR, reading any Data Register, or writing to
the MSR or CSR. The INT bit is not affected by
the state of the IE bit in the MSR.
All Conversions Complete bit. When high, this
status bit indicates that conversions have been
completed on all channels selected in the CSR.
It is cleared by reading any of the Data Regis-
ters or by writing to the MSR or CSR. In 10-bit
mode, ACC = 1 implies that the DV bits of all
active channels are true (see Data Registers).
This bit is often used in Modes 2 and 3. In Mode
1, ACC will only be set if conversions are explic-
itly invoked (via writes to the SAR) for each
channel selected in the CSR.
Conversion In Progress bit. This bit is logically
high when a conversion is initiated and goes low
when a conversion completes. In the scanning
modes, Modes 2 and 3, CIP will go low momen-
tarily between successive channels and cannot
be used in lieu of ACC in Mode 2.
NOTE: Following a write of $00 to the SAR, to
terminate Mode 3 conversions, CIP may remain
high until cleared with a write to the MSR or the
CSR or with the read of a Data Register or with
a write to the SAR with ENC or SAE = 1. CIP = 1
is not a true indication of an ongoing conversion.
See “Mode 3 - Continuous Scan”
Channel Address Register, bit 2. CA2, CA1,
and CA0 form a three bit binary number that
indicates the current contents of the CAR. The
CAR is originally set by the user via the SAR
(see SAR). The CAR is automatically incre-
mented following reads of Data Registers and
following conversions in the scanning modes
(Modes 2 and 3). The Status Register can be
read at any time. Reading CA2 - CA0 during
Modes 2 and 3 will produce changing channel
addresses as the conversions proceed.
CIP
5
4
0
CA2
3
CA1
2
CA0
1
0
0
$13