CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 6

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

Serial Communications
Hardware Interface
All communications between the A2 and the controlling
processor are carried out over the Serial Peripheral Interface
(SPI) bus lines (MOSI, MISO, SCK, and CE). The SPI bus is
directly compatible with the SPI facilities of Intersil’
CDP68HC05 microcontrollers. Data is transmitted over the
MISO and MOSI lines synchronous with SCK. Transfers are
done most significant bit first.
The A2 acts as a “slave” device. The controlling “master” sig-
nals the A2 that a SPI transfer is to take place by raising CE
and clocking SCK. A single shift register is used for transfer-
ring data in and out of the A2. Whenever CE and SCK are
activated, data is shifted from the master to the A2 over the
Master-Out-Slave-In (MOSI) line and, simultaneously, during
read operations, data is shifted to the master from the A2
over the Master-In-Slave-Out (MISO) line. Note that SCK
must be provided by the master for both reads and writes.
To accommodate various hardware systems, the A2 can
shift data on either the rising or falling edge of SCK. The
“active” edge is automatically determined by the A2. At the
moment that CE is first brought to a high level, the state of
(READ
ONLY)
SCK a
SCK
MOSI
MISO
CE
b
T
dsu
T
dh
$0E
$0F
$00
$01
$10
$11
$12
$13
T
P
D7
CONTROL/STATUS REGISTERS
CHANNEL SELECT REGISTER
START ADDRESS REGISTER
MODE SELECT REGISTER
FIGURE 2. TIMING DIAGRAM FOR SERIAL PERIPHERAL INTERFACE
HIGH DATA REGISTER 0
HIGH DATA REGISTER 7
LOW DATA REGISTER 0
LOW DATA REGISTER 7
FIGURE 1. A PROGRAMMER’S MODEL OF THE CDP68HC68A2
STATUS REGISTER
DATA REGISTERS
D6
T
dod
D5
CDP68HC68A2
D4
6
SCK is latched. This latched state determines the interpreta-
tion of SCK. If SCK is low when CE is activated, data is
shifted out on MISO on each rising edge of SCK and data is
latched from MOSI on each falling edge of SCK (see SCK
in Figure 2). If SCK is high when CE is activated, data is
shifted out on MISO on each falling edge of SCK and data is
latched from MOSI on each rising edge of SCK (see SCK
Figure 2).
Hardware Interfacing to CDP68HC05 Controllers
When interfacing the A2 to CDP68HC05 controllers, set
CPHA = 1 and CPOL = (0 or 1) in the SPI control register.
Note that SCK pulses are generated only when data is written
to the SPI Data Register in a CDP68HC05. Reading data from
or writing data to the A2 requires writing data to the SPI Data
Register. The data will be ignored by the A2 for read opera-
tions. The read data is available to the CDP68HC05 in the SPI
Data Register when SPIF is true in the SPI Status Register.
Hardware Interfacing to Non-CDP68HC05 Controllers
Most popular microcontrollers have a synchronous commu-
nications facility which can be adapted to work with the A2.
Those that don’t can be easily interfaced using port lines to
synthesize a SPI bus.
CHANNEL ADDRESS REGISTER
D3
OUT
TO
A
D
D2
IN
TO
M
U
X
8
1
D1
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
D0
b
in
a