CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 5

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

Through this specification the CDP68HC68A2 is referred to
simply as the A2.
Functional Pin Description
OSC - Oscillator (Input/Output)
This pin is user programmable. In the “external” mode, the
clock input for the successive approximation logic is applied
to OSC from an external clock source. The input is a Schmitt
trigger input which provides excellent noise immunity. In the
“internal” mode, a capacitor is connected between this pin
and a power supply to form a “one pin oscillator”. The
frequency of the oscillator is inversely dependent on the
capacitor value. Differences in period, from one device to
another, should be anticipated. Systems utilizing the internal
oscillator must be tolerant of uncertainties in conversion
times or provide trimming capability on the OSC capacitor.
See Table 2 for typical frequencies versus capacitance.
INT - Interrupt (Open Drain Output)
INT is used to signal the completion of an A/D conversion.
This output is generally connected, in parallel with a pullup
resistor, to the interrupt input of the controlling microproces-
sor. The open drain feature allows wire-NOR’ing with other
interrupt inputs. The inactive state of INT is high impedance.
When active, INT is driven to a low level output voltage. The
state of INT is controlled and monitored by bits in the Mode
Select and Status Registers.
MISO - Master-In-Slave-Out (Output)
Serial data is shifted out on this pin. Data is provided most
significant bit first.
MOSI - Master-Out-Slave-In (Input)
Serial data is shifted in on this pin. Data must be supplied
most significant bit first. This is a CMOS input and must be
held high or low at all times to minimize device current.
SCK - Serial Clock (Input)
Serial data is shifted out on MISO, synchronously, with each
leading edge of SCK. Input data from the MOSI pin is
latched, synchronously, with each trailing edge of SCK.
CE - Chip Enable (Input)
An active HIGH device enable. CE is used to synchronize
communications on the SPI lines (MOSI, MISO, and SCK).
When CE is held in a low state, the SPI logic is placed in a
reset mode with MISO held in a high impedance state.
Following a transition from low to high on CE, the
CDP68HC68A2 interprets the first byte transferred on the
SPI lines as an address. If CE is maintained high,
subsequent transfers are interpreted as data reads or writes.
AIO/EXT REF - Analog Input 0/External Reference (Input)
This input is one of eight analog input channels. Its function
is selectable through the Mode Select Register (MSR). If VR
is set high in the MSR, AI0/EXT REF provides an external
voltage reference against which all other inputs are
CDP68HC68A2
5
measured. AI0/EXT REF must fall within the V
supply rails. If VR is set low in the MSR, V
reference voltage and AI0/EXT REF is treated as any other
analog input (see AI1-AI7).
AI1-AI7 - Analog Inputs 1-7 (Inputs)
Together with AI0/EXT REF, these pins provide the eight
analog inputs (channels) which are multiplexed within the
CDP68HC68A2 to a single, high-speed, successive approxi-
mation, A/D converter. AI1-AI7 must fall within the V
V
V
This pin provides the negative analog reference and the
negative power supply for the CDP68HC68A2.
V
This pin provides the positive power supply and, depending
on the value of the VR bit in the MSR, the positive analog
reference for the CDP68HC68A2.
Overview
From the programmer’s perspective, the A2 is comprised of
three control registers (Mode Select Register - MSR,
Channel Select Register - CSR, and Starting Address
Register - SAR), a status register (SR), an array of eight
pairs of Data Registers, and one non-addressable, internal
register (Channel Address Register). See Figure 1.
The A2 contains a high speed, 10-bit, successive
approximation, analog to digital converter (A/D). The input to
the A/D can be any one of the A2’s eight analog inputs (AI0
through AI7). The contents of the CAR determine which ana-
log input is connected to the A/D. The result of each analog
to digital conversion is written to the Data Register array. The
Data Register array is also addressed by the contents of the
CAR, providing a one to one correspondence between each
analog input and each Data Register pair.
The contents of the CAR are also used during Data Register
reads to address the Data Register array. The CAR is
automatically jammed with the correct address when an
Address/Control Byte is sent to the A2. A second means, to
initialize the CAR, is by writing to the SAR.
Normal procedure for programming the A2 is to first select
the desired hardware mode by writing to the MSR. The
“active” analog channels are then specified by writing to the
CSR (channels not selected in the CSR are skipped during
conversions and burst mode reads). Finally, a write to the
SAR initializes the CAR (designating the first channel to
convert) and initiates the A/D conversions.
Polling of the SR or hardware interrupts can be used to
determine the completion of conversions.
The converted data is read from the data registers. In eight
bit mode, a single register is read for each channel of inter-
est. In ten bit mode, two registers are read per channel.
DD
SS
DD
- Negative Power Supply
supply rails.
- Positive Power Supply
DD
is used as the
SS
and V
SS
and
DD