CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 11

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

When all channels have been converted the INT and ACC
flags in the SR are set, the INT pin is driven low (if IE is true
in the MSR), the CIP flag is cleared, and, if active, the
internal oscillator is disabled.
Data Registers can safely be read after all channels have
been converted. If the starting channel was a channel active
in the CSR then the CAR will one again be pointing to that
channel (providing all channels had been read or CSR or
MSR written since the last set of conversions - see Note
below). IF a read from a Data Register, other than the one
first converted, is performed, the CAR must be set to the
desired register prior to sending the Address/Control Byte.
Setting CAR is done by writing the SAR with ENC = 0, SAE
= 1, and the CA2 - CA0 bits equal to the desired channel.
NOTE: A write to the SAR does not clear the DV flag for each chan-
nel. This implies that if: conversions are completed on all registers
selected in CSR; conversions stopped; an incomplete read of the
Data Registers is performed; and conversions reinitiated with a write
to the SAR - some DVs will still be set. In Mode 2, which terminates
when all DVs are true (ACC goes true), unread channels may not be
converted unless CSR is written to before setting ENC.
There are two ways to prematurely stop conversions in Mode
2. The first is to perform any “abort” action (see Abort Modes).
Performing an abort, may produce spurious conversion val-
ues. The second, and preferred means to stop a Mode 2 con-
version, is to clear the ENC bit by writing a $00 to the SAR.
Clearing ENC will synchronously stop conversions at the end
of the current conversion. When prematurely stopping conver-
sions, CIP is not valid. The CIP flag cannot be used to deter-
mine when the current conversion is complete. Instead, a time
delay equal to one conversion time must be built into the soft-
ware. The appropriate delay will ensure the last conversion is
complete before Data Register reads begin.
Prematurely stopping the conversions leaves the CAR in an
unknown state. One remaining task, before Data Registers
are read, is to be certain the contents of the CAR match the
address sent in the Address/Control Byte. This is done by
jamming the CAR with a write to the SAR with ENC = 0,
SAE = 1, CA3 - C A2 - CA0 equal to the desired channel
address.
Mode 3 - Continuous Scan
In Mode 3, when ENC is set in the SAR, conversions are
performed on all channels selected in the CSR. COnversion
begin on the channel specified by the CAR (this channel
does not have to be active in the CSR) and proceed in
ascending order for all channels selected in the CSR. Each
time the highest active channel is done converting, the CAR
advances to the lowest active channel and continues from
that point.
When ENC is set in the SAR, the internal clock is activated
(if selected) and conversions begin.
When all channels have been converted one time the ACC
flag in the SR is set. This is the only valid status flag in Mode
3. The CIP flag is not valid in Mode 3. The INT flag and the
INT pin are both held in a disabled state during Mode 3.
Data Registers cannot be read until Mode 3 conversions
have been terminated. There are two ways to stop
CDP68HC68A2
11
conversions in Mode 3. The first is to perform any “abort”
action (see Abort Modes). Performing an abort, may pro-
duce spurious conversion values. The second, and preferred
means to stop a Mode 3 conversion, is to clear the ENC bit
by writing a $00 to the SAR. Clearing ENC will
synchronously stop conversions at the end of the current
conversion. CIP is not valid following the clearing of ENC.
The CIP flag cannot be used to determine when the current
conversion is complete. Instead, a time delay equal to one
conversion time must be built into the software. The
appropriate delay will ensure the last conversion is complete
before Data Register reads begin.
The Data Registers can safely be read after ENC is cleared
and one conversion time has elapsed. One remaining task is
to be certain the contents of the CAR match the address
sent in the Address/Control Byte. This is done by jamming
the CAR with a write to the SAR with ENC = 0, SAE = 1, and
CA2 - CA0 equal to the desired channel address.
Abort Modes
Any active mode can be aborted by any one of the following
means:
The contents of Data Registers are not guaranteed following
an abort. Writing a $00 to the MSR is equivalent to a reset.
To synchronously stop conversions in Modes 2 or 3 set the
SAR to $00 (See Mode 2 and Mode 3).
Analog Inputs
Shown in Figure 5 is a simplified equivalent circuit represent-
ing the input to the Analog to Digital Converter through the
multiplexer as seen from each AIn pin.
Due to the nature of the switched capacitor array used by the
successive approximation A/D, two important points are
noted here:
It is recommended to set the conversion oscillator frequency
in accordance with the input impedance in order to allow
sufficient time (the 1.5 T
waveform through the modeled input low pass filter network
which includes the input source in a series circuit with the
internal impedance.
1. A write to the MSR
2. A write to the CSR
3. A write to the SAR with ENC and/or SAE = 1
4. A read of any Data Register
1. A property of capacitive input is the intrinsic sample and
2. The input to the capacitor network appears as an RC
hold function. This provides all that is necessary to
accurately sample a point on an input waveform within
the input bandwidth shown in the specifications (under
1.5 conversion oscillator cycles).
network with a time constant and therefore places
constraints on the source impedance. The charging time
and therefore the accuracy of the conversion will be ad-
versely affected by increasing the source impedance.
OSC
cycles) to sample a changing