CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet - Page 8

• Manufacturer Part Number: CDP68HC68A2M
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: Intersil Corporation

Mode Select Register (MSR)
Address/Control: (R/W)0010000 - $10
Read/Write: Yes
The read/write register is used to select the various modes
of operation of the A2. Bits 6 and 7 are “don’t cares” and can
be set as either 1 or 0. The functions of bits 0 through 5 are
as follows:
B5, EXT
B4, VR
B3, M8
B2, IE
B1, M1
B0, M0
7
0
M1
0
0
1
1
6
0
The External Oscillator bit (EXT) is used to
select between an external or an internal (single
pin oscillator) clock source at pin 1 (OSC) of the
A2. If EXT is low, an external clock is selected
and the OSC pin functions as an input. If EXT is
high, an internal clock is selected and the OSC
pin functions as a one pin oscillator. See Table 2
for typical frequencies of the internal oscillator.
The Voltage Reference (VR) bit is used to select
the source of the voltage reference. When VR is
0, V
A/D converter. When VR is 1, the voltage at AI0
serves as the full scale reference for the A/D
converter. When VR = 1, the digital reading of
any active channel which exceeds the AI0 refer-
ence voltage will be “clipped” to the full scale
value of $3FF ($FF for 8-bit mode).
The Eight Bit Mode (M8) bit selects either 10-bit
or 8-bit as the mode of operation. A low (0) in
this bit enables the 10-bit mode, while a high (1)
enables the 8-bit mode.
The Interrupt Enable (IE) bit is used to enable
the INT output function on pin 2. A low (0) dis-
ables the interrupt function and maintains INT in
a high impedance state. A high enables the
interrupt function, allowing INT to be driven low
at the appropriate times in Modes 1 and 2.
Mode Select, bit 1. This bit is used along with
M0 to select the conversion mode, shown in
Table 1, of the A/D converter.
Mode Select, bit 0. This bit is used along with
M1 to select the conversion mode, shown in
Table 1, of the A/D converter.
M2
0
1
0
1
TABLE 1. CONVERSION MODES
EXT
DD
5
is used as the full scale reference for the
MODE
VR
4
0
1
2
3
M8
3
Idle
Single Conversion
Single Scan
Continuous Scan
IE
2
DESCRIPTION
M1
1
M0
0
CDP68HC68A2
$10
8
Channel Address Register (CAR)
Address/Control: Not Addressable
The CAR contains the address of the next channel to
convert during Modes 1, 2, and 3. During multiple byte reads
of the Data Registers, the CAR contains the address of the
channel to read and is advanced, to the next higher active
channel, following each read. When advancing, the CAR
skips any channel not selected in the CSR. After
incrementing to the highest active channel, the CAR will
return to the lowest active channel.
The CAR is not directly accessible. It can be jammed via a
write to the SAR or by transmitting an Address/Control Byte
which addresses any Data Register. Note: addressing a
Data Register to set the CAR is valid only under certain
circumstances - see the following boxed caution. When
jamming the CAR via the SAR, the specified channel does
not need to be selected in the CSR. The CAR’s contents are
read as part of the SR. See the descriptions of the SAR and
the SR for details.
NOTE: CAUTION! When addressing Data Registers, the user must
ensure that the contents of the CAR match the address portion of the
Address/Control Byte. Failure to do so may result in corrupted data.
This condition is generally met in Modes 1 and 2. When running in
Mode 3 special care must be taken to meet this requirement. See fur-
ther explanation under SAR, SR, Modes, and Applications Information.
Channel Select Register (CSR)
Address/Control: (R/W)0010001 - $11
Read/Write: Yes
This read/write register is used to designate the active
analog input channels. Channels which are not active will be
skipped during conversions and multiple byte reads, unless
specifically selected by writing to the SAR. Setting a bit high
in CSR selects the associated channel, while setting a bit
low deselects the channel. Each Cn bit in the CSR corre-
sponds to an AIn pin on the A2 device. Example: setting C7
= C4 = 1 and setting all other bits to 0 will select AI7 and AI4
as inputs to the A/D multiplexer.
Starting Address Register (SAR)
Address/Control: (R/W)0010010 - $12
Read/Write: Yes
This register is used to enable conversions in all modes and
to set the address of the current channel in the CAR. Prior
to, or simultaneously with, enabling conversions, the CAR
must be set to a known state via the SAR. Once set, the
contents of the CAR determine the first channel to be
converted when conversions are enabled - hence the name
“Starting Address Register”. The CAR may be jammed with
ENC
C7
7
7
C6
6
6
0
C5
5
5
0
SAE
C4
4
4
CA2
C3
3
3
CA1
C2
2
2
CA0
C1
1
1
H/L
C0
0
0
$11
$12