ISL6530/31EVAL1 INTERSIL [Intersil Corporation], ISL6530/31EVAL1 Datasheet - Page 14

• Manufacturer Part Number: ISL6530/31EVAL1
• Description: Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination
• Manufacturer: INTERSIL [Intersil Corporation]

current (see the equations below). These equations assume
linear voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are dissipated
by the ISL6531 and don't heat the MOSFETs. However, large
gate-charge increases the switching interval, t
increases the MOSFET switching losses.
Ensure that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heat sink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised when using devices
with very low gate thresholds (V
protection circuitry may be circumvented by these
MOSFETs. Very high dv/dt transitions on the phase node
may cause the Miller capacitance to couple the lower gate
with the phase node and cause an undesireable turn on of
the lower MOSFET while the upper MOSFET is on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 10. The
boot capacitor, C
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
boot diode drop, V
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
LOSSES WHILE SINKING CURRENT
LOSSES WHILE SOURCING CURRENT
Q
GATE
P
P
P
P
LOWER
UPPER
UPPER
LOWER
Where: D is the duty cycle = V
=
C
= Io
= Io
=
=
t
f
BOOT
SW
s
Io
2
BOOT
Io
is the switching frequency.
2
2
x r
x r
2
is the combined switch ON and OFF time, and
BOOT
×
×
DS(ON)
×
DS(ON)
D
r
r
DS ON
(
, plus the voltage rise across Q
DS ON
conducts, to a voltage of VCC less the
V
BOOT1
(
, develops a floating supply voltage
(
x D
x (1 - D)
)
)
×
×
D
14
–
(
1 D
V
+
–
TH
BOOT2
1
-- - Io
2
OUT
⋅
)
). The shoot-through
+
/ V
×
1
-- - Io
2
)
V
IN
⋅
IN
,
×
×
SW
V
t
SW
IN
which
×
×
t
f
SW
s
LOWER
×
f
s
.
ISL6531
where Q
MOSFET, C
the bootstrap voltage immediately before turn-on, and
V
The bootstrap capacitor begins its refresh cycle when the
gate drive begins to turn-off the upper MOSFET. A refresh
cycle ends when the upper MOSFET is turned on again,
which varies depending on the switching frequency and
duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the previous equation and solving for CBOOT.
Typical gate charge values for MOSFETs considered in
these types of applications range from 20 to 100nC. Since
the voltage drop across Q
simply VCC - V
minimize the voltage drop across the bootstrap capacitor
during the on-time of the upper MOSFET. Initial calculations
with V
bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1µF. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
C
BOOT2
BOOT
+
-
ISL6531
BOOT2
FIGURE 10. UPPER GATE DRIVE BOOTSTRAP
≥
GATE
is the bootstrap voltage immediately after turn-on.
---------------------------------------------------- -
V
BOOT1
BOOT
no less than 4V will quickly help narrow the
is the maximum total gate charge of the upper
Q
D
. A schottky diode is recommended to
GATE
GND
–
is the bootstrap capacitance, V
UGATEn
PHASEn
V
BOOTn
LGATEn
D
BOOT2
BOOT
VCC
g
LOWER
, of 100nC. Limiting the voltage
C
+
V
-
BOOT
D
is negligible, V
Q
Q
V
UPPER
LOWER
IN
NOTE:
V
NOTE:
V
G-S
G-S
RR
BOOT1
≈ V
BOOT1
≈ V
, would
CC
CC
-V
is
is
D