HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 47

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type
SuperH™ architecture SH-3 CPU as its core that has peripheral functions required for system
configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code
level. This LSI incorporates a memory management unit (MMU) that has a 128-entry 4-way set
associative translation lookaside buffer (TLB).
The LSI incorporates the following peripheral functions: an on-chip direct memory access
controller (DMAC) that enables high-speed data transfer and a bus state controller (BSC) that
enables direct connection to different types of memory. The LSI also incorporates a serial
communication interface, an A/D converter, a D/A converter, a timer, and a realtime clock that
enable system configuration at low cost.
A built-in power management function enables dynamic control of power consumption. Thus, this
LSI is optimum for portable electronic devices such as PDAs that require both high performance
and low power.
The SH7706 incorporates a user debugging interface (H-UDI) and an advanced user debugger
(AUD) to support emulator functions such as E10A. This LSI also incorporates a user break
controller (UBC) for self debugging.
Note: * The SuperH is a trademark of Renesas Technology, Corp.
1.1
Original Renesas SuperH architecture
Object code level compatible with SH-1, SH-2 and SH-3
32-bit RISC-type instruction set
Five-stage pipeline
Instruction execution time: one instruction/cycle for basic instructions
General-register: Sixteen 32-bit general registers
Control-register: Eight 32-bit control registers
System-register: Four 32-bit system registers
32-bit internal data bus
Logical address space: 4 Gbytes
Instruction length: 16-bit fixed length
Improved code efficiency
Load-store architecture
Delayed branch instructions
Instruction set oriented for C language
Feature
Section 1 Overview
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