HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 65

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: The M, Q, S and T bits can be set or cleared by special instructions in user mode. Their
Bit
11, 10
9
8
7
6
5
4
3, 2
1
0
Saved Status Register (SSR)
Stores current SR value at time of exception to indicate processor status in return to instruction
stream from exception handler.
Initialized to undefined by a reset.
Saved Program Counter (SPC)
Stores current PC value at time of exception to indicate return address at completion of
exception handling.
Initialized to undefined by a reset.
values are undefined after a reset. All other bits can be read or written in privileged mode.
Bit
Name
M
Q
I3
I2
I1
I0
S
T
Initial Value
All 0
1
1
1
1
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits always read as 0, and the write
value should always be 0.
M bit
Q bit
Used by the DIV0S/U and DIV1 instructions.
Interrupt mask bits
4-bit field indicating the interrupt request mask
level.
I3 to I0 do not change to the interrupt
acceptance level when an interrupt is occurred.
Reserved
These bits always read as 0, and the write
value should always be 0.
S bit
Used by the MAC instruction.
T bit
Used by the MOVT, CMP/cond, TAS, TST, BT,
BF, SETT, CLRT, and DT instructions to
indicate true (1) or false (0).
Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1,
NEGC, SHAR/L, SHLR/L, ROTR/L, and
ROTCR/L instructions to indicate a carry,
borrow, overflow, or underflow.
Rev. 4.00, 03/04, page 19 of 660