M58LW032C110ZA6 STMICROELECTRONICS [STMicroelectronics], M58LW032C110ZA6 Datasheet
M58LW032C110ZA6
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M58LW032C110ZA6 Summary of contents
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... Asynchronous Page Mode Read 90/25ns, 110/25ns – Random Read 90ns, 110ns PROGRAMMING TIME – 16 Word Write Buffer – 12µs Word effective programming time 32 UNIFORM 64 KWord MEMORY BLOCKS ENHANCED SECURITY – Block Protection/ Unprotection – Smart Protection: irreversible block locking system – V ...
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M58LW032C TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program/Erase Controller Status Bit (SR7 Erase Suspend Status Bit ( SR6 Erase Status Bit (SR5) ...
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M58LW032C Reserved (SR0 ...
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Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The user segment can be protected. The Reset/Power-Down pin is used to apply a Hardware Reset to the memory and to set the de- vice in power-down mode. The device features an Auto Low Power mode. If the bus becomes inactive during Asynchronous Read operations, the device automatically enters Auto Low Power mode. In this mode the power consumption is reduced to the Auto Low Power supply current ...
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Figure 2. Logic Diagram DDQ 21 A1-A21 V PEN W E M58LW032C SSQ Table 1. Signal Names A1-A21 DQ0-DQ15 STS DQ0-DQ15 RP V STS ...
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M58LW032C Figure 3. TSOP56 Connections 8/ A21 A20 A19 A18 A17 A16 V DD A15 A14 A13 A12 M58LW032C V PEN A11 A10 ...
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Figure 4. TBGA64 Connections (Top view through package DQ8 DQ1 F K DQ0 PEN A13 A14 ...
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M58LW032C Figure 5. Block Addresses Total Mbit Blocks Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses. 10/61 Word (x16) Bus Width 1FFFFFh 1 Mbit or 64 KWords 1F0000h 1EFFFFh 1 ...
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... Valid Data Ready (R). The Valid Data Ready output open drain output that can be used to identify if the memory is ready to output data or not. The Valid Data Ready output is only active during Synchronous Burst Read operations when the Burst Length is set to Continuous. The Valid ...
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... Program/Erase Controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. V Supply Voltage supply to the internal core of the memory device the main power supply for all operations (Read, Program and Erase). V Supply Voltage. V DDQ ...
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... Bus Write, Output Disable, Power-Down and Standby. See Table 2, Bus Operations, for a sum- mary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Address Latch. Address latch operations input valid addresses. ...
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... Read AC Characteristics, for details. Asynchronous Page Read. In Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page is 4 Words and has the same A3-A22, only A1 and A2 may change. The first read operation within the Page has the ...
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... CR2-CR0). In Synchronous Continuous Burst Read mode one Burst Read operation can access the entire memory sequentially. If the starting ad- dress is not associated with a page (4 Word) boundary the Valid Data Ready, R, output goes Low indicate that the data will not be ready IL in time and additional wait-states are required ...
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... M58LW032C CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. The Configuration Register bits are de- scribed in Table 3. They specify the selection of the burst length, burst type, burst X and Y laten- cies and the Read operation. See figures 6 and 7 for examples of Synchronous Burst Read configu- rations ...
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Table 3. Configuration Register Address Mnemonic Bit Name Bit 16 CR15 Read Select 15 CR14 14 to CR13-CR11 X-Latency 12 Internal 11 CR10 Clock Divider 10 CR9 Y-Latency Valid Data 9 CR8 Ready 8 CR7 Burst Type Valid Clock 7 ...
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M58LW032C Table 4. Burst Type Definition Starting x4 x4 Address Sequential Interleaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 4 – – 5 – – 6 – – 7 – – 8 – – Figure ...
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Figure 7. Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2 VALID NV NV=NOT VALID M58LW032C VALID NV VALID NV VALID NV ...
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... M58LW032C COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below. After power- Reset operation the memory enters Read mode ...
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... Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an er- ...
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... Two Bus Write cycles are required to issue the Set Configuration Register command. Once the com- mand is issued the memory returns to Read mode Read Memory Array command had been is- sued. The value for the Configuration Register is pre- sented on A1-A16. CR0 is on A1, CR1 on A2, etc.; ...
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... Table 5. Commands Command Read Memory Array 2 Read Electronic Signature 2 Read Status Register 2 Read Query 2 Clear Status Register 1 Block Erase 2 Word Program 2 Write to Buffer and Write Program Program/Erase Suspend 1 Program/Erase Resume 1 Set Configuration Register 2 Block Protect 2 Blocks Unprotect 2 Protection Register 2 Program ...
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... Description The STS pin is Low during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. Supplies a system interrupt pulse at the end of a Block Erase operation. Supplies a system interrupt pulse at the end of a Program operation. ...
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... Figure 8. Protection Register Memory Map WORD ADDRESS Table 9. Program, Erase Times and Program Erase Endurance Cycles Parameters Block (1Mb) Erase Chip Program (Write to Buffer) Chip Erase Time Program Write Buffer Word/Byte Program Time (Word/Byte Program command) Program Suspend Latency Time Erase Suspend Latency Time ...
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... When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The ...
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... V , the Program/Erase Controller is active or has OL completed its operation; when the bit is High Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is sued the Program Suspend Status bit returns Low. ...
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M58LW032C Table 10. Status Register Bits OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend ...
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MAXIMUM RATING Stressing the device above the ratings listed in Ta- ble 11, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
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M58LW032C DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests ...
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Table 14. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Burst Read) DDB I Supply Current (Standby) DD1 I Supply Current (Auto Low-Power) DD5 I ...
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M58LW032C Figure 11. Asynchronous Bus Read AC Waveforms A1-A21 DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 15. Asynchronous Bus Read AC Characteristics. Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid ...
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Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms A1-A21 tAVLL L tLHLL E G DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol t Address Valid to Latch Enable Low AVLL ...
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M58LW032C Figure 13. Asynchronous Page Read AC Waveforms A1-A2 A3-A21 DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Table 17. Asynchronous Page Read AC Characteristics Symbol t Address Transition to Output Transition AXQX1 t Address Valid to Output ...
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Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled A1-A21 E L tELWL G tGHWL W DQ0-DQ15 RB V PEN Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled A1-A21 L tELLL E tELWL G tGHWL W DQ0-DQ15 ...
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M58LW032C Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled. Symbol t Address Valid to Latch Enable High AVLH t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH ...
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Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled A1-A21 W tWLEL G tGHEL E L DQ0-DQ15 RB V PEN Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled A1-A21 L tWLLL W tWLEL G tGHEL E DQ0-DQ15 ...
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M58LW032C Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled Symbol t Address Valid to Latch Enable High AVLH t Address Valid to Chip Enable High AVEH t Data Input Valid to Chip Enable High DVEH ...
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Figure 18. Synchronous Burst Read AC Waveform Note: Valid Clock Edge = Rising (CR6 = 1) M58LW032C 39/61 ...
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M58LW032C Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output K (2) Output Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = Valid output, NV= Not ...
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Figure 20. Reset, Power-Down and Power-up AC Waveform DQ0-DQ15 tPHQV RB RP tVDHPH VDD, VDDQ Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-Down High to Data Valid PHQV t Reset/Power-Down Low to Reset/Power-Down High ...
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M58LW032C PACKAGE MECHANICAL Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 22. TSOP56 - 56 lead Plastic Thin Small Outline ...
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Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline BALL "A1" A Note: Drawing is not to scale. Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data Symbol Typ ...
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... E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. ...
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APPENDIX A. BLOCK ADDRESS TABLE Table 25. Block Addresses Block Address Range Number (x16 Bus Width) 32 1F0000h-1FFFFFh 31 1E0000h-1EFFFFh 30 1D0000h-1DFFFFh 29 1C0000h-1CFFFFh 28 1B0000h-1BFFFFh 27 1A0000h-1AFFFFh 26 190000h-19FFFFh 25 180000h-18FFFFh 24 170000h-17FFFFh 23 160000h-16FFFFh 22 150000h-15FFFFh 21 140000h-14FFFFh ...
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... APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... Not Available Data n 16h n where 2 is number of bytes memory Size 01h Device Interface 00h Organization Sync./Async. 05h Maximum number of bytes in Write Buffer, 2 00h 01h Bit7-0 = number of Erase Block Regions in device 1Fh Number (n-1) of Erase Blocks of identical size ...
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M58LW032C Table 30. Block Status Register Address A21-A1 (1) (BA+2)h Note specifies the block address location, A21-A17. 2. Not Supported. 48/61 Data 0 Block UnProtected bit0 1 Block Protected 0 Last erase operation ended successfully bit1 1 Last ...
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Table 31. Extended Query information Address Address offset A21-A2 (P)h 31h (P+1)h 32h (P+2)h 33h (P+3)h 34h (P+4)h 35h (P+5)h 36h (P+6)h 37h (P+7)h 38h (P+8)h 39h (P+9)h 3Ah (P+A)h 3Bh (P+B)h 3Ch (P+C)h 3Dh (P+D)h 3Eh (P+E)h 3Fh (P+F)h ...
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M58LW032C APPENDIX C. FLOW CHARTS Figure 23. Write to Buffer and Program Flowchart and Pseudo Code Note 1: N+1 is number of Words to be programmed Note 2: Next Program Address must have same A5-A21. Note 3: A full Status ...
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... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while SR7 = 1 If SR2 = 0, Program completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume erasure – ...
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... NO Erase to Protected Block Error Erase command: – write 20h – write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command) do: – read status register – if Program/Erase Suspend command given execute suspend erase loop while SR7 = 1 If SR3 = 1, V PEN invalid error: – ...
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... B0h – write 70h do: – read status register while SR7 = 1 If SR6 = 0, Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...
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... Block Protect Command – write 60h, Block Adress – write 01h, Block Adress do: – read status register while SR7 = 1 If SR3 = 1, V PEN Invalid Error If SR4 = 1, SR5 = 1 Invalid Command Sequence Error If SR4 = 1, Block Protect Error Read Memory Array Command: – write FFh AI06157b ...
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... Block Adress – write D0h, Block Adress do: – read status register while SR7 = 1 If SR3 = 1, V PEN Invalid Error If SR4 = 1, SR5 = 1 Invalid Command Sequence Error If SR5 = 1, Blocks Unprotect Error Read Memory Array Command: – write FFh M58LW032C AI06158b 55/61 ...
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... Protection Register Address, Protection Register Data do: – read status register while SR7 = 1 If SR3 = 1, SR4 = 1 V PEN Invalid Error If SR1 = 0, SR4 = 1 Protection Register Program Error If SR1 = 1, SR4 = 1 Program Error due to Protection Register Protection Read Memory Array Command: – write FFh AI06159b ...
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Figure 30. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ 98h SIGNATURE YES CFI QUERY B Note 1. The Erase command (20h) can only be issued if the flash is not already ...
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M58LW032C Figure 31. Command Interface and Program Erase Controller Flowchart (b) WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY PROGRAM BUFFER LOAD NO PROGRAM D0h COMMAND ERROR YES c 58/61 B READ STATUS READ ARRAY YES NO FFh ...
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Figure 32. Command Interface and Program Erase Controller Flowchart (c). WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY READ ARRAY B READ STATUS READ ARRAY YES NO FFh NO YES PROGRAM SUSPENDED YES YES 70h NO YES 90h ...
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M58LW032C REVISION HISTORY Table 32. Document Revision History Date Version 11-Mar-2002 -01 First Issue (Data Brief) 10-Jul-2002 -02 Document expanded to full Product Preview Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...