M58LW032C110ZA6 STMICROELECTRONICS [STMicroelectronics], M58LW032C110ZA6 Datasheet - Page 11

• Manufacturer Part Number: M58LW032C110ZA6
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 11, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable and Latch Enable must be low when
selecting the addresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
low, V
Erase or Program operation.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, V
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
is high, V
low, V
active the Ready/Busy status is given on DQ7.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
V
consumption to the Standby level, I
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at V
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Down pin can be used to apply a Hardware Reset
to the memory.
IH
deselects the memory and reduces the power
IL
IL
IL
, the data bus outputs data from the mem-
. The address is internally latched in an
. When the Program/Erase Controller is
IH,
or the Reset/Power-Down signal is
DD1
Reset/Power-
.
IH
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V
Reset/Power-Down is Low, V
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, V
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the Ready/
Busy pin stays low, V
t
Power-Down pulse.
After Reset/Power-Down goes High, V
memory will be ready for Bus Read and Bus Write
operations after t
does not fall during a reset, see Ready/Busy Out-
put section.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
Erase or Program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
Latch Enable (L). The Bus Interface is config-
ured to latch the Address Inputs on the rising edge
of Latch Enable, L. In synchronous bus operations
the address is latched on the active edge of the
Clock when Latch Enable is Low, V
ing of Latch Enable, whichever occurs first. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, V
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, V
whichever occurs first.
During asynchronous bus operations the Clock is
not used.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
one cycle before. Valid Data Ready Low, V
PLPH
+ t
IL
, or on the rising edge of Latch Enable,
PHRH,
until the completion of the Reset/
IL
, the latch is transparent.
PHQV
IL
IL
, for at least t
, for a maximum timing of
. Note that Ready/Busy
IL
, the Status Regis-
IL
,during a Block
M58LW032C
IL
or on the ris-
PLPH
. When
IH
OL
, the
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