M58LW032C110ZA6 STMICROELECTRONICS [STMicroelectronics], M58LW032C110ZA6 Datasheet - Page 13

• Manufacturer Part Number: M58LW032C110ZA6
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

BUS OPERATIONS
There are six standard bus operations that control
the device. These are Address Latch, Bus Read,
Bus Write, Output Disable, Power-Down and
Standby. See Table 2, Bus Operations, for a sum-
mary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Address Latch. Address latch operations input
valid addresses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, V
Enable High, V
ing edge of Address Latch.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address Inputs, applying a Low
signal, V
Latch Enable and keeping Write Enable High, V
The data read depends on the previous command
written to the memory (see Command Interface
section). See Figures 11, 12, 13, 18 and 19 Read
AC Waveforms, and Tables 15, 16, 17 and 20
Read AC Characteristics, for details of when the
output becomes valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch addresses and input
data to be programmed.
Table 2. Bus Operations
Note: 1. X = Don’t Care V
Output Disable
Address Latch
2. Depends on G
Power-Down
Operation
Bus Read
Bus Write
Standby
IL
, to Chip Enable, Output Enable and
IH
; the address is latched on the ris-
IL
or V
IH
V
V
V
V
V
E
X
IH
.
IL
IL
IL
IL
IL
and keeping Write
V
V
V
G
X
X
X
IH
IH
IL
V
V
V
V
W
X
X
IH
IH
IH
IL
IH
.
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and setting
Latch Enable Low, V
latched by the Command Interface on the rising
edge of Chip Enable or Write Enable, whichever
occurs first. The Data Inputs/Outputs are latched
by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
the Bus Write operation.
See Figures 14, 15, 16 and 17, Write AC Wave-
forms, and Tables 18 and 19, Write AC Character-
istics, for details of the timing requirements.
Output Disable. The The Data Inputs/Outputs
are high impedance when the Output Enable is at
V
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
independent of Chip Enable, Output Enable or
Write Enable.
Standby. Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
when Chip Enable is at V
tion is reduced to the standby level I
outputs are set to high impedance, independently
from the Output Enable or Write Enable inputs.
If Chip Enable switches to V
erase operation, the device enters Standby mode
when finished.
IH
.
V
V
V
DD2
L
X
X
X
IL
IL
IL
, and the outputs are high impedance,
Address
Address
Address
A1-A21
X
X
X
IL
. The Address Inputs are
IH
. The power consump-
IH
Data Output or Hi-Z
during a program or
Data Output
DQ0-DQ15
Data Input
M58LW032C
High Z
High Z
High Z
DD1
IH
and the
, during
13/61
(2)