M58LW032C110ZA6 STMICROELECTRONICS [STMicroelectronics], M58LW032C110ZA6 Datasheet - Page 26

• Manufacturer Part Number: M58LW032C110ZA6
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58LW032C
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
The Status Register can only be read using Asyn-
chronous Bus Read or Single Synchronous Read
operations. Once the memory returns to Read
Memory Array mode the bus will resume the set-
ting in the Configuration Register automatically.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
(Chip Enable, V
able and Output Enable, V
Status Register bits SR5, SR4, SR3 and SR1 are
associated with various error conditions and can
only be reset with the Clear Status Register com-
mand. The Status Register bits are summarized in
Table 10, Status Register Bits. Refer to Table 10
in conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
tus bit is Low, V
is active and all other Status Register bits are High
Impedance; when the bit is High, V
gram/Erase Controller is inactive.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status Bit ( SR6). The
Suspend Status bit indicates that an Erase opera-
tion has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
26/61
IH
OL
) and then reactivating (Chip En-
, the Program/Erase Controller
IL
) the device.
OH
, the Pro-
Erase
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, V
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is High, V
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit
can be used to identify if the memory has failed to
verify that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, V
ory has successfully verified that the block has
erased correctly or all blocks have been unprotect-
ed successfully. When the Erase Status bit is
High, V
pending on the cause of the failure other Status
Register bits may also be set to High, V
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status Bit (SR4). The Program Status
bit is used to identify a Program or Block Protect
failure. The Program Status bit should be read
once the Program/Erase Controller Status bit is
High (Program/Erase Controller inactive).
When the Program Status bit is Low, V
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
V
OH
If only the Erase Status bit (SR5) is set High,
V
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully.
If the failure is due to an erase or blocks
unprotect with V
bit (SR3) is also set High, V
If the failure is due to an erase on a protected
block then Block Protection Status bit (SR1) is
also set High, V
If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (SR4) is also set High, V
OH
, the program or block protect operation has
, then the Program/Erase Controller has
OH
, the erase operation has failed. De-
OH
PEN
.
low, V
OL
OH
, then V
.
OL
OH
PEN
, the mem-
OH
.
.
OL
Status
OH
, the
OL
, a
,