M58LW032C110ZA6 STMICROELECTRONICS [STMicroelectronics], M58LW032C110ZA6 Datasheet - Page 14

• Manufacturer Part Number: M58LW032C110ZA6
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58LW032C
READ MODES
Read operations can be performed in two different
ways depending on the settings in the Configura-
tion Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is asynchro-
nous; if the data output is synchronized with clock,
the read operation is synchronous.
The read mode and format of the data output are
determined by the Configuration Register. (See
Configuration Register section for details).
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Read mode.
Asynchronous Read Modes
In Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corre-
sponding to the address latched, that is the mem-
ory array, Status Register, Common Flash
Interface, Electronic Signature or Block Protection
Status depending on the command issued. CR15
in the Configuration Register must be set to ‘1’ for
asynchronous operations.
During Asynchronous Read operations, if the bus
is inactive for a time equivalent to t
vice automatically enters Auto Low Power mode.
In this mode the internal supply current is reduced
to the Auto Low Power supply current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Asynchronous Read operations can be performed
in three different ways, Asynchronous Latch Con-
trolled Read, Asynchronous Random Read and
Asynchronous Page Read.
Asynchronous Latch Controlled Read.
In Asynchronous Latch Controlled Read opera-
tions read the address is latched in the memory
before the value is output on the data bus, allowing
the address to change during the cycle without af-
fecting the address that the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, V
Enable High, V
ing edge of Address Latch. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
V
see Figure 12, Asynchronous Latch Controlled
Read AC Waveforms and Table 16, Asynchro-
nous Latch Controlled Read AC Characteristics for
details on when the output becomes valid.
See Figures 12, Asynchronous Latch Controlled
Read AC Waveforms, and Table 16, Asynchro-
nous Latch Controlled Read AC Characteristics,
for details.
14/61
IL
, to read the data on the Data Inputs/Outputs;
IH
; the address is latched on the ris-
IL
and keeping Write
AVQV
DD5
, the de-
. The
Asynchronous Random Read. As the Latch En-
able input is transparent when set Low, V
chronous Random Read operations can be
performed by holding Latch Enable Low, V
throughout the bus operation.
See Figures 11, Asynchronous Random Read AC
Waveforms, and Table 15, Asynchronous Ran-
dom Read AC Characteristics, for details.
Asynchronous Page Read. In
Page Read mode a Page of data is internally read
and stored in a Page Buffer. Each memory page is
4 Words and has the same A3-A22, only A1 and
A2 may change.
The first read operation within the Page has the
normal access time (t
within the same Page have much shorter access
times (t
mal, longer timings apply again.
See Figures 13, Asynchronous Page Read AC
Waveforms, and Table 17, Asynchronous Page
Read AC Characteristics, for details.
Synchronous Read Modes
In Synchronous Read mode the data output is syn-
chronized with the clock. CR15 in the Configura-
tion Register must be set to ‘0’ for synchronous
operations.
Synchronous Burst Read. In
Burst Read mode the data is output in bursts syn-
chronized with the clock. It is possible to perform
burst reads across bank boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read opera-
tions, such as Read Status Register, Read CFI,
Read Electronic Signature and Block Protection
Status, Single Synchronous Read or Asynchro-
nous Read must be used.
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are con-
figured in the Configuration Register.
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, V
Latch Enable are Low, V
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
by setting Output Enable Low, V
and 7 for examples of Synchronous Burst Read
operations.
The number of Words to be output during a Syn-
chronous Burst Read operation can be configured
as 4 Words, 8 Words or Continuous (Burst Length
AVQV1
). If the Page changes then the nor-
AVQV
IH
IL
, and Chip Enable and
, during the active edge
), subsequent reads
IL
. See Figures 6
Asynchronous
Synchronous
IL
, Asyn-
IL