ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 277

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

27.8.7
27.8.8
27.8.9
2545T–AVR–05/11
Setting the boot loader lock bits by SPM
EEPROM write prevents writing to SPMCSR
Reading the fuse and lock bits from software
RWWSB by writing the RWWSRE. See
page 279
To set the Boot Loader Lock bits and general lock bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
See
Boot Loader bits affect the Flash access.
If bits 5..0 in R0 are cleared (zero), the corresponding Boot Lock bit and general lock bit will be
programmed if an SPM instruction is executed within four cycles after BLBSET and SELFPR-
GEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for future
compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the
lO
writing the Lock bits. When programming the Lock bits the entire Flash can be read during the
operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to
for a detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
Bit
R0
Bit
Rd
Bit
Rd
ck
bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when
Table 27-2 on page 273
for an example.
Manual.
FLB7
7
7
1
7
–
FLB6
6
6
1
6
–
and
BLB12
BLB12
FLB5
Table 27-3 on page 273
5
5
5
“Simple assembly code example for a boot loader” on
BLB11
BLB11
FLB4
4
4
4
BLB02
BLB02
FLB3
3
3
3
for how the different settings of the
BLB01
BLB01
ATmega48/88/168
FLB2
2
2
2
FLB1
LB2
LB2
Table 28-5 on page 287
1
1
1
FLB0
LB1
LB1
0
0
0
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