LPC1767 NXP [NXP Semiconductors], LPC1767 Datasheet - Page 18

• Manufacturer Part Number: LPC1767
• Description: 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC1769_68_67_66_65_64_4
Product data sheet
7.7.1 Features
7.7.2 Interrupt sources
7.7 Nested Vectored Interrupt Controller (NVIC)
7.8 Pin connect block
7.9 General purpose DMA controller
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both.
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB (LPC1769/68/66/65/64 only) and Ethernet controllers (LPC1769/68/67/66/64
only) and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1,
all UARTs, the I
can be used to trigger DMA transfers. Note that the I
available on the LPC1764.
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Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 33 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt (NMI)
Software interrupt generation
2
S-bus interface, the ADC, and the DAC. Two match signals for each timer
Rev. 04 — 1 February 2010
LPC1769/68/67/66/65/64
32-bit ARM Cortex-M3 microcontroller
2
S-bus interface and the DAC are not
© NXP B.V. 2010. All rights reserved.
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