LPC1767 NXP [NXP Semiconductors], LPC1767 Datasheet - Page 33

• Manufacturer Part Number: LPC1767
• Description: 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC1769_68_67_66_65_64_4
Product data sheet
7.29.6.1 Sleep mode
7.29.6.2 Deep-sleep mode
7.29.6 Power control
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of V
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
The LPC17xx support a variety of power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, Peripheral Power Control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all
dynamic power use in any peripherals that are not required for the application. Each of the
peripherals has its own clock divider which provides even better power control.
Integrated PMU (Power Management Unit) automatically adjust internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
The LPC17xx also implement a separate power domain to allow turning off power to the
bulk of the device while maintaining operation of the RTC and a small set of registers for
storing data during any of the power-down modes.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.
The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later.
The RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
DD(3V3)
Rev. 04 — 1 February 2010
ramp (in the case of power on), the type of crystal and its
LPC1769/68/67/66/65/64
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2010. All rights reserved.
33 of 66