AK5700VN AKM [Asahi Kasei Microsystems], AK5700VN Datasheet - Page 23

• Manufacturer Part Number: AK5700VN
• Description: 16-Bit ?? Mono ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(See Table 6).
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
Table 7).
In DSP Mode 0, BCLK and LRCK start to output corresponding to Ach data after PLL goes to lock state by setting
PMPLL bit = “0”
becomes shorter by 1/(256fs) than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC outputs invalid data when
the PLL is unlocked.
MS0569-E-01
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
Others
Mode
0
1
2
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
FS3 bit
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
“1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0, BCLK “H” time of the first pulse
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
0
0
1
Don’t care
“1”
FS2 bit
0
1
MCKO bit = “0”
Others
“L” Output
“L” Output
“L” Output
Don’t care
Don’t care
Don’t care
FS1 bit
“1”
MCKO pin
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MCKO bit = “0”
Don’t care
Don’t care
Don’t care
“L” Output
“L” Output
“L” Output
FS0 bit
MCKO bit = “1”
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
See Table 9
Invalid
Invalid
MCKO pin
Sampling Frequency
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
7.35kHz ≤ fs ≤ 12kHz
MCKO bit = “1”
See Table 9
Invalid
Invalid
See Table 10
“L” Output
Range
BCLK pin
N/A
Invalid
“L” Output
1fs Output
LRCK pin
Default
Invalid
[AK5700]
2006/12
“1”.