AK5700VN AKM [Asahi Kasei Microsystems], AK5700VN Datasheet - Page 25

• Manufacturer Part Number: AK5700VN
• Description: 16-Bit ?? Mono ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
A reference clock of PLL is selected among the input clocks to MCKI, EXBCLK or EXLRCK pin. The required clock to
the AK5700 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).
a) PLL reference clock: MCKI pin
EXBCLK and EXLRCK inputs should be synchronized with MCKO output. The phase between MCKO and EXLRCK
dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by
MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5).
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation
(PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
should be in the power-down mode (PMADC bit = “0”).
b) PLL reference clock: EXBCLK or EXLRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).
MS0569-E-01
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK pin)
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
AK5700
AK5700
MCKI
MCKO
EXBCLK
EXLRCK
SDTO
MCKI
EXBCLK
EXLRCK
SDTO
256fs/128fs/64fs/32fs
≥ 32fs
1fs
32fs, 64fs
- 25 -
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
1fs
MCLK
BCLK
LRCK
SDTI
BCLK
LRCK
SDTI
DSP or μP
DSP or μP
[AK5700]
2006/12