AK5700VN AKM [Asahi Kasei Microsystems], AK5700VN Datasheet - Page 41

• Manufacturer Part Number: AK5700VN
• Description: 16-Bit ?? Mono ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
MS0569-E-01
Addr
11H
Addr
10H
Register Definitions
PMADC: MIC-Amp and ADC Power Management
PMVCM: VCOM Power Management
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When PMVCM, PMADC, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values remain
unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin should be “L”.
When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be
present.
PMPLL: PLL Power Management
M/S: Master / Slave Mode Select
PLL3-0: PLL Reference Clock Select (See Table 4)
0: Power down (Default)
1: Power up
0: Power down (Default)
1: Power up
0: EXT Mode and Power Down (Default)
1: PLL Mode and Power up
0: Slave Mode (Default)
1: Master Mode
Default: “1001”(MCKI pin=12MHz)
Register Name
PLL Control
Register Name
Power Management
Default
When the PMADC bit is changed from “0” to “1”, the initialization cycle (3088/fs=70.0ms@fs= 44.1kHz,
HPF1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when PMADC=PMPLL=PMMP=MCKO bits = “0”.
Default
D7
D7
0
0
0
0
D6
0
0
D6
0
0
D5
PLL3
0
0
- 41 -
D5
1
D4
PLL2
0
0
D4
0
D3
0
0
PLL1
D3
0
PMVCM
D2
PLL0
0
D2
1
D1
M/S
0
0
D1
0
[AK5700]
PMADC
2006/12
PMPLL
D0
0
D0
0