AK5700VN AKM [Asahi Kasei Microsystems], AK5700VN Datasheet - Page 49

• Manufacturer Part Number: AK5700VN
• Description: 16-Bit ?? Mono ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
When ADC is powered-up, the clocks must be supplied.
MS0569-E-01
Power Supply
PMVCM bit
(Addr:10H, D2)
(Addr:16H, D2)
(Addr:11H, D0)
(Addr:11H, D1)
Clock Set up
PMPLL bit
BCLK pin
LRCK pin
MCKO pin
1. PLL Master Mode.
MCKO bit
<Example>
MCKI pin
PDN pin
M/S bit
(1) After Power Up, PDN pin “L”
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows.
(3) Power UpVCOM: PMVCM bit = “0”
(4) In case of using MCKO output: MCKO bit = “1”
(5) PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source.
(6) The AK5700 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
“L” time of 150ns or more is needed to reset the AK5700.
(2a) M/S bit = “1” and setting of PLL3-0, FS3-0, BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
VCOM should first be powered-up before the other block operates.
In case of not using MCKO output: MCKO bit = “0”
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
starts.
(1)
(2)
(3)
(4)
(5)
Figure 41. Clock Set Up Sequence (1)
40msec(max)
(7)
40msec(max)
“H”
CONTROL SEQUENCE
Input
“1”
(6)
(8)
- 49 -
Output
Output
Example:
(1) Power Supply & PDN pin = “L”
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Audio I/F Format: I2S
MCKO: Enable
Sampling Frequency: 44.1kHz
MCKO, BCLK and LRCK output
(2)Addr:11H, Data:12H
(4)Addr:16H, Data:04H
(3)Addr:10H, Data:04H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:11H, Data:13H
[AK5700]
“H”
2006/12