FM93C86 Fairchild Semiconductor, FM93C86 Datasheet - Page 7

• Manufacturer Part Number: FM93C86
• Description: 16K-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus)
• Manufacturer: Fairchild Semiconductor

FM93C86A Rev. C.1
Write Disable (WDS) instruction disables all programming opera-
tions and should follow all programming operations. Executing
this instruction after a valid write instruction would protect against
accidental data disturb due to spurious noise, glitches, inadvert-
ent writes etc. Input information (Start bit, Opcode and Address)
for this WDS instruction should be issued as listed under Table 1
or Table 2. The device becomes write-disabled at the end of this
cycle when the CS signal is brought low. Execution of a READ
instruction is independent of WDS instruction. Refer Write Disable
cycle diagram.
The ERASE instruction will program all bits in the specified
location to logical “1” state. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table 1 or Table 2. The self-timed programming cycle starts
with the clocking of the last data bit (DO). It takes t
appropriate DC and AC Electrical Characteristics table) for the
internal programming cycle to finish. During this time, the device
remains busy and is not ready for another instruction. Status of the
internal programming can be polled as described under WRITE
instruction description. While the device is busy, it is recom-
mended that no new instruction be issued. Refer Erase cycle
diagram.
The Erase all instruction will program all locations to logical “1”
state. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table 1 or Table
WP
time (Refer
2. The self-timed programming cycle starts with the clocking of the
last data bit (DO). It takes t
Electrical Characteristics table) for the internal programming
cycle to finish. During this time, the device remains busy and is not
ready for another instruction. Status of the internal programming
can be polled as described under WRITE instruction description.
While the device is busy, it is recommended that no new instruc-
tion be issued. Refer Erase All cycle diagram.
instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The
“ERASE” and “ERASE ALL” instructions are included to maintain compatibility with
earlier technology EEPROMs.
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-
PROM.
The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL”
WP
time (Refer appropriate DC and AC
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