74AC373SC Fairchild Semiconductor, 74AC373SC Datasheet - Page 2

• Manufacturer Part Number: 74AC373SC
• Description: IC LATCH OCTAL 3 STATE 20-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74ACr
• Type: D-Typer

Specifications of 74AC373SC

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 6 V
• Independent Circuits: 1
• Delay Time - Propagation: 7ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: AC
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: SOIC W
• Propagation Delay Time: 15ns
• Operating Supply Voltage (typ): 2.5/3.3/5V
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
Connection Diagram
Pin Description
Functional Description
The AC/ACT373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard
outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
D
LE
OE
O
0
0
–D
–O
Pin Names
7
7
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
n
Description
inputs enters the latches.
2
Logic Symbols
Truth Table
H
L
Z
X
O
of Latch Enable
0
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
LE
Previous O
X
H
H
L
0
Inputs
before HIGH-to-LOW transition
OE
H
L
L
L
IEEE/IEC
D
H
X
X
L
n
www.fairchildsemi.com
Outputs
O
O
H
Z
L
n
0