PCD5003AH Philips Semiconductors, PCD5003AH Datasheet
PCD5003AH
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PCD5003AH Summary of contents
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DATA SHEET PCD5003A Enhanced Pager Decoder for POCSAG Product specification File under Integrated Circuits, IC17 INTEGRATED CIRCUITS 1999 Jan 08 ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Introduction 7.2 The POCSAG paging code 7.3 Error correction 7.4 Operating states 7.5 ON status 7.6 OFF status 7.7 Reset 7.8 Bit rates 7.9 Oscillator 7.10 Input data processing 7.11 Battery saving 7.12 Synchronization strategy 7 ...
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... On-chip SRAM buffer for message data 4 ORDERING INFORMATION TYPE NUMBER NAME PCD5003AH LQFP32 plastic low profile quad flat package; 32 leads; body 7 1999 Jan 08 2 Slave I C-bus interface to microcontroller for transfer of message data, status/control and EEPROM ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 5 BLOCK DIAGRAM handbook, full pagewidth 26 ZSD 27 SYNTHESIZER ZSC CONTROL 28 ZLE 24 RXE RECEIVER 25 CONTROL ROE DATA FILTER 23 AND RDI CLOCK RECOVERY 3 CLOCK DON CONTROL 16 TS1 TEST 20 CONTROL TS2 18 XTAL1 17 XTAL2 1999 Jan 08 EEPROM EEPROM CONTROL ...
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... DQC RDI RXE ROE ZSD ZSC ZLE V SS VIB LED ATH ATL 1 ALC 2 DON 3 REF 4 PCD5003AH INT 5 n.c. 6 RST Fig.2 Pin configuration. 5 Product specification PCD5003A DESCRIPTION 16 test input 1 (normally LOW by internal pull-down) 17 decoder crystal oscillator output 18 decoder crystal oscillator input ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7 FUNCTIONAL DESCRIPTION 7.1 Introduction The PCD5003A is a very low power decoder and pager controller specifically designed for use in new generation radio pagers. The architecture of the PCD5003A allows for flexible application in a wide variety of radio pager designs. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Alert-only calls only consist of a single address code-word. Numeric and alphanumeric calls have message code-words following the address. A message causes the frame structure to be temporarily suspended. Message code-words are sent until the message is completed, with only the sync words being transmitted in their expected positions ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 1 POCSAG recommended call types and function bits BIT 20 (MSB 7.3 Error correction Table 2 Error correction ITEM Preamble Synchronization code-word Address code-word Message code-word 7.4 Operating states The PCD5003A has 2 operating states: ON status OFF status. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.8 Bit rates The PCD5003A can be configured for data rates of 512, 1200 or 2400 bits/s by SPF programming. These data rates are derived from a single 76.8 kHz oscillator frequency. 7.9 Oscillator The oscillator circuit is designed to operate at 76.8 kHz. Typically, a tuning fork crystal will be used as a frequency source ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG If any message code-word is found to be uncorrectable, ‘data-fail’ mode is entered and no data transfer will be attempted at the next sync word position. Instead, a test for sync word will be carried out. In the data fail mode message reception continues normally for 1 batch duration ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.16 Sync word indication The sync word recognized by the PCD5003A is shown in the call header (bits S3 to S1). The decimal value represents the identifier number in the EEPROM of the UPSW in question. A value of 7 indicates the standard POCSAG sync word. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 4 Call header format BIT 7 BYTE NUMBER (MSB Table 5 Call header bit identification BITS (MSB TO LSB and Note 1. The DF bit in the call header is set: a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard POCSAG or a user-programmed sync word ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 9 Call terminator bit identification BITS (MSB TO LSB Note 1. The DF bit in the call terminator is set: a) When any call data code-word in the terminating batch was uncorrectable, while in ‘data receive’ mode. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.21 Demodulator quick charge Two modes of operation are available that determine the periods when the DQC is set. The operating mode is selected by EEPROM programming of SPF byte 3, bit D5: Mode 0 (D5 = 0): DQC is active (logic HIGH) during the receiver establishment time t RXE except data receive and data fail ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 11 Receiver and oscillator establishment times (note 1) CONTROL ESTABLISHMENT TIME OUTPUT RXE 5 10 ROE 20 30 Note 1. The exact values may differ slightly from the above values, depending on the bit rate (see Table 22). 7.23 Synthesizer control ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG handbook, full pagewidth MSB 0 ZSD ZSC ZLE handbook, full pagewidth MSB SDA S SCL 1 2 START ADDRESS 1999 Jan 08 t ZSD ZCL t ZDS Fig.6 Synthesizer interface timing. LSB N MSB A INTERRUPT SERVICING ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG FROM handbook, full pagewidth MASTER (a) S SLAVE ADDRESS (b) S SLAVE ADDRESS (c) S SL. ADR. R/W 0 (write) (a) Master writes to slave. (b) Master reads from slave. (c) Combined format (shown: write plus read). 2 7.25 Decoder I C-bus access All internal access to the PCD5003A takes place via the ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 13 Index register (1) ADDRESS 00H 00H 01H 02H 03H 04H 05H 05H 06H 07H 08H 09H 0AH 0BH to 0FH Notes 1. The index register only uses the least significant nibble, the upper 4 bits are ignored. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.28 Status/control register The status/control register consists of two independent registers, one for reading (status) and one for writing (control). The status register shows the current operating condition of the decoder and the cause( external interrupt. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.29 Pending interrupts A secondary status register is used for storing status bits of pending interrupts. This occurs: When a new call is received while the previous one was not yet acknowledged by reading the status register When an interrupt occurs during a status read operation. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.33 Received call delay Call reception causes both the periodic interrupt modulus and the counter register to be reset. Since the periodic interrupt counter runs for another 2.55 seconds after a reset, the received call delay 1 (in second units) can be determined by reading the counter register. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.34 Alert generation The PCD5003A is capable of controlling 3 different alert transducers: acoustic beeper (HIGH and LOW level), LED and vibrator motor. The associated outputs are ATH/ATL, LED and VIB respectively. ATL is an open drain output capable of directly driving an acoustic alerter via a resistor. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.42 Cancelling alerts Standard POCSAG alerts (manual or automatic) are cancelled by resetting bit D0 in the alert set-up register. User defined alerts are cancelled by writing a zero to the alert cadence register. Any ongoing alert is cancelled when a reset pulse is applied to input RST. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.44 SRAM access The on-chip SRAM can hold bytes of call data. Each call consists of a call header (3 bytes), message data blocks (3 bytes per code-word) and a call terminator (3 bytes). The RAM is filled by the decoder and can be read via the ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.51 EEPROM access limitations Since the EEPROM address pointer is used during data decoding, the EEPROM may not be accessed while the receiver is active (RXE = 1 advised to switch to OFF state before accessing the EEPROM. The EEPROM cannot be written unless the EEPROM programming enable bit (bit D1) in the control register is set ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 19 Unused EEPROM addresses ROW Note 1. When using bytes 04H and 05H, care must be taken to preserve the SPF information stored in bytes 00H to 03H. Table 20 Special programmed functions (EEPROM address 00H) BIT (MSB: D7) ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 22 Establishment time as a function of bit rate NOMINAL ESTABLISHMENT 512 BITS/s TIME bits 11 bits 15 bits 23.4 ms (12 bits 31.2 ms (16 bits 39.1 ms (20 bits 46.9 ms (24 bits) Table 23 Special programmed functions (EEPROM address 02H) ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 7.58 Synthesizer programming data Data for programming a PLL synthesizer via pins ZSD, ZSC and ZLE can be stored in row 1 of the EEPROM. Six bytes are available starting from address 08H. Data is transferred in two serial blocks of 24 bits each, starting with bit 0 (MSB) of block 1 ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG Table 27 Identifier bit allocation BYTE BIT (MSB: D7 and Notes 1. The bit numbering corresponds with the numbering in a POCSAG code-word: bit 1 is the flag bit (0 = address message UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0 ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 8 OPERATING INSTRUCTIONS 8.1 Reset conditions When the PCD5003A is reset by applying a HIGH-level on input RST, the condition of the decoder is as follows: OFF status (irrespective of DON input level) REF output frequency 32768 Hz All internal counters reset Status/control register reset ...
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Acrobat reader. white to force landscape pages to be ... XTAL1 RST asynchronous t RST REF active LOW INT active HIGH V clk RXE ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG handbook, full pagewidth DON ZSC ZLE RXE Fig.13 Start-up timing including synthesizer programming. 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER V supply voltage DD V external reference voltage input PR V voltage on pins ALC, DON, RST, SDA and SCL V ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 10 DC CHARACTERISTICS SYMBOL PARAMETER Supplies V supply voltage DD V external reference voltage input programming supply voltage DD(prog) I supply current (OFF) DD0 I supply current (ON) DD1 I programming supply current DD(prog) Inputs ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG SYMBOL PARAMETER I HIGH level output current OH VIB and LED ATH INT and REF ZSD, ZSC and ZLE ATL ROE, RXE and DQC Notes 1. Inputs: SDA and SCL pulled Outputs: RXE and ROE logic 0; REF: f Oscillator: no crystal ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 14 AC CHARACTERISTICS SYMBOLS PARAMETER System clock T system clock period clk Call alert frequencies f alert frequency AL f warbled alert; modulation AW frequency f warbled alert; high acoustic AWH alert frequency f warbled alert; low acoustic alert ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG SYMBOLS PARAMETER Receiver control t RXE, ROE transition time RXT t RXE establishment time RXON (nominal values: actual duration is bit rate dependent, see Table 22) t ROE establishment time ROON (nominal values: actual duration is bit rate dependent, ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG SYMBOLS PARAMETER POCSAG data timing (1200 bits/s) f data input rate DI t bit duration BIT t code-word duration CW t preamble duration PA t batch duration BAT POCSAG data timing (2400 bits/s) f data input rate DI t bit duration ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG handbook, halfpage handbook, full pagewidth 1999 Jan 08 t DI1 t DI0 t TDI Fig.14 Data input timing. t RFP t RFP 2t RFP Fig.15 Timing of the 32768 Hz reference signal. 38 Product specification PCD5003A MGL100 MLC278 ...
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Acrobat reader. white to force landscape pages to be ... BATTERY POSITIVE V ANT ATL ATH VIB DATA RDI OUT BAT RECEIVER BAT REF ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 16 PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.60 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 17 SOLDERING 17.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 17.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE BGA, SQFP HLQFP, HSQFP, HSOP, SMS (3) PLCC , SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect) ...
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... Philips Semiconductors Enhanced Pager Decoder for POCSAG 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains fi ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...