PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 18

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 13 Index register
Notes
1. The index register only uses the least significant nibble, the upper 4 bits are ignored.
2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.
7.26
The PCD5003A can signal events to an external controller
via an interrupt signal on output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
Interrupts are generated by the following events (more
than one event possible):
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position, if data fail mode (short fade recovery
mode in APOC1) is not active.
1999 Jan 08
Call data available for output (bit D2)
SRAM pointers becoming equal (bit D3)
Expiry of periodic time-out (bit D7)
Expiry of alert time-out (bit D4)
Change of state in out-of-range indicator (bit D5)
Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Enhanced Pager Decoder for POCSAG
External interrupt
ADDRESS
0BH to 0FH
0AH
00H
00H
01H
02H
03H
04H
05H
05H
06H
07H
08H
09H
(1)
real-time clock:
EEPROM data input/output
RAM write address pointer
RAM read address pointer
periodic interrupt modulus
EEPROM address pointer
periodic interrupt counter
real-time clock: seconds
REGISTER FUNCTION
RAM data output
alert cadence
alert set-up
unused
control
status
18
The interrupt output INT is reset after completion of a
status read operation.
7.27
In the PCD5003A certain interrupts can be suppressed by
masking via the control register. This feature prevents
unnecessary wake-up actions of the microcontroller
causing battery life reduction.
The following interrupts can be masked:
Although no interrupts are generated by these conditions
when masked via the control register, the corresponding
status bits are normally updated and available via the
status register. At reset the control register is cleared,
causing all interrupts to be enabled.
1
100
Out-of-Range (status bit D5): change of state
interrupt, masked by setting control register bit D5
interrupt (source selected by control register bit D2),
masked by setting control register bit D6
Periodic Timer (status bit D7): timer overflow interrupt,
masked by setting control register bit D7.
BAT/RXE monitoring (status bit D6): change of state
second
Interrupt Masking
ACCESS
note 2
R/W
R/W
R/W
R/W
R/W
Product specification
W
W
W
W
R
R
R
R
PCD5003A