PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 29

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 27 Identifier bit allocation
Notes
1. The bit numbering corresponds with the numbering in a POCSAG code-word: bit 1 is the flag bit (0 = address,
2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0; bits 2 to 19 contain
3. Bits FR3 to FR1 (MSB : FR3) contain the 3 least significant bits of the 21-bit RIC.
4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.
7.60
An on-chip voltage doubler provides an unregulated
DC output for supplying an LCD or a low power
microcontroller on output V
capacitor of typical 100 nF is required between pins CCN
and CCP. The voltage doubler is enabled via SPF
programming.
7.61
All interface lines are suited for communication with a
microcontroller operating from a higher supply voltage.
The external device must have a common reference at V
of the PCD5003A.
The reference voltage for the level-shifted interface must
be applied to input V
doubler output V
has a separate (regulated) supply this separate supply
voltage should be connected to V
1999 Jan 08
Enhanced Pager Decoder for POCSAG
1 = message).
the identifier bit pattern; they are followed by 2 predetermined random (function) bits and the UPSW is completed by
10 CRC error correction bits and an even-parity bit.
Voltage doubler
Level-shifted interface
BYTE
1
2
3
PO
if required. When the microcontroller
PR
. This could be the on-chip voltage
BIT (MSB: D7)
D7 and D6
PO
D7 to D0
D7 to D0
. An external ceramic
D5
D4
D3
D2
D1
D0
PR
.
bits 2 to 9 of POCSAG code-word (RIC or UPSW); notes 1 and 2
bits 10 to 17
bits 18 and 19
frame number bit FR3 (RIC); note 3
frame number bit FR2 (RIC)
frame number bit FR1 (RIC)
identifier type selection (0 = UPSW, 1 = RIC); note 4
identifier enable (1 = enabled)
reserved for future use, logic 0 when read
SS
29
The level-shifted interface lines are: RST, DON, ALC, REF
and INT.
The I
level-shifted independently of V
standard external pull-up resistors.
7.62
A special ‘signal test’ mode is available for monitoring the
performance of a receiver circuit together with the
front-end of the PCD5003A.
For this purpose the output of the digital noise filter and the
recovered bit clock are made available at outputs REF and
INT respectively. All synchronization and decoding
functions are normally active.
The ‘signal test’ mode is activated/deactivated by SPF
programming.
2
C-bus interface lines SDA and SCL can be
Signal test mode
DESCRIPTION
PR
by means of the
Product specification
PCD5003A