PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 25

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.51
Since the EEPROM address pointer is used during data
decoding, the EEPROM may not be accessed while the
receiver is active (RXE = 1). It is advised to switch to OFF
state before accessing the EEPROM.
The EEPROM cannot be written unless the EEPROM
programming enable bit (bit D1) in the control register is
set.
For writing a minimum programming supply voltage
V
current (I
Any modified SPF settings (bytes 0 to 3) only take effect
after a decoder reset. Modified identifiers are active
immediately.
7.52
EEPROM read operations must start at a valid address in
the non-contiguous memory map. Single-byte or block
reads are permitted.
7.53
EEPROM write operations must always take place in
blocks of 6 bytes, starting at the beginning of a row.
Programming a single byte will reset the other bytes in the
same row. Modifying a single byte in a row requires
re-writing the unchanged bytes with their old contents.
1999 Jan 08
handbook, full pagewidth
DD(prog)
Enhanced Pager Decoder for POCSAG
EEPROM access limitations
EEPROM read operation
EEPROM write operation
is required (2.0 V typ.). The programming supply
DD(prog)
ROW
) needed during writing will be
0
1
2
3
4
5
6
7
D
0
1
I
SPF bits
D
2
1
I
COLUMN
D
2
3
I
Fig.11 EEPROM organization and access.
Synthesizer data
D
4
3
I
500 A.
D
5
4
I
D
6
5
I
25
After writing each block a pause of maximum 7.5 ms is
required to complete the programming operation
internally. During this time the external microcontroller
may generate an I
transfer is started the decoder will pull SCL LOW during
this pause.
After writing the EEPROM programming enable bit (D1) in
the control register must be reset.
7.54
When an invalid write address is used, the column counter
bits (D2 to D0) are forced to zero before being loaded into
the address pointer. The row counter bits are used
normally.
7.55
A programming sequence may be aborted by an I
stop condition. Next, the EEPROM programming enable
bit (D1) in the control register must be reset.
Any bytes received of the last 6-byte block will be ignored
and the contents of this (incomplete) EEPROM block will
remain unchanged.
7.56
A total of 20 EEPROM bytes is available for general
purpose storage (see Table 19).
Identifiers
Invalid write address
Incomplete programming sequence
Unused EEPROM locations
D7
D7
I/O REGISTER
0
2
C-bus stop condition. If another I
ADDRESS
POINTER
1
unused bytes
ROW COLUMN
0
1
0
MLC254
D0
D0
0
Product specification
PCD5003A
2
2
C-bus
C-bus