PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 22

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.34
The PCD5003A is capable of controlling 3 different alert
transducers: acoustic beeper (HIGH and LOW level), LED
and vibrator motor. The associated outputs are ATH/ATL,
LED and VIB respectively. ATL is an open drain output
capable of directly driving an acoustic alerter via a resistor.
The other outputs require external transistors.
Each alert output can be individually enabled via the alert
set-up register. Alert level and warble can be separately
selected. The alert pattern can either be standard
POCSAG or determined via the alert cadence register.
Direct alert control is possible via input ALC.
The alert set-up register is shown in Table 18.
Standard POCSAG alerts can be selected by setting
bit D0 in the alert set-up register, bits D6 and D7
determining the alert pattern used.
Automatic generation via all alert outputs of the POCSAG
alert pattern matching the received call type can be
enabled by SPF programming (SPF byte 3, bit D2).
7.35
When not programmed for POCSAG alerts (alert set-up
register bit D0 = 0), the 8-bit alert cadence register
determines the alert pattern. Each bit represents a
62.5 ms time slot, a logic 1 activating the enabled alert
transducers. The bit pattern is rotated with the
MSB (bit D7) being output first and the LSB (bit D0) last.
When the last time slot (bit D0) is started an interrupt is
generated to allow loading of a new pattern. When the
pattern is not changed it will be repeated. Writing a zero to
the alert cadence register will halt alert generation.
7.36
Acoustic alerts are generated via outputs ATL and ATH.
For LOW level alerts only ATL is active, while for HIGH
level alerts ATH is also active. ATL is driven in counter
phase with ATH.
The alert level is controlled by bit D1 of the alert set-up
register.
When D1 is reset, for standard POCSAG alerts (D0 = 1) a
LOW level acoustic alert is generated during the first
4 seconds (ATL), followed by 12 seconds at HIGH level
(ATL + ATH). When D1 is set, the full 16 seconds are at
HIGH level. An interrupt is generated upon expiry of the full
alert time.
1999 Jan 08
Enhanced Pager Decoder for POCSAG
Alert generation
Alert cadence register (03H; write)
Acoustic alert
22
When using the alert cadence register, D1 would normally
be updated by external control when the alert time-out
interrupt occurs at the start of the 8th cadence time slot.
Since D1 acts immediately on the alert level, it is advised
to reset the last bit of the previous pattern to prevent
unwanted audible level changes.
7.37
The vibrator output (VIB) is activated continuously during
a standard POCSAG alert or whenever the alert cadence
register is non-zero.
Two alert levels are supported: LOW level (25 Hz
square-wave) and HIGH level (continuous). The vibrator
level is controlled by bit D1 in the alert set-up register.
7.38
The LED output pattern corresponds either to the selected
POCSAG alert or to the contents of the alert cadence
register. No equivalent exists for HIGH/LOW level alerts.
7.39
When enabled by setting bit D2 in the alert set-up register,
the signals on outputs ATL, ATH and LED are warbled with
a 16 Hz modulation frequency. Output LED is switched on
and off at the modulation rate, while outputs ATL and ATH
switch between f
7.40
A direct alert control input (ALC) is available for generating
user alarm signals (e.g. battery-low warning). A HIGH level
on input ALC activates all enabled alert outputs, overruling
any ongoing alert patterns.
7.41
Generation of a standard POCSAG alert (D0 = 1)
overrides any alert pattern in the alert cadence register.
After completion of the standard alert, the original cadence
is restarted from the position it was left at. The alert set-up
register will now contain the settings for the standard alert.
The highest priority has been assigned to the alert control
input (ALC). All enabled alert outputs will be activated
while ALC is set. Outputs are activated/deactivated
synchronous with the decoder clock. Activation requires
an extra delay of 1 clock when no alerts are being
generated.
When input ALC is reset, acoustic alerting does not cease
until the current output frequency cycle has been
completed.
Vibrator alert
LED alert
Warbled alert
Direct alert control
Alert priority
AWH
and f
AWL
alerter frequencies.
Product specification
PCD5003A