PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 6

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7
7.1
The PCD5003A is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5003A allows for
flexible application in a wide variety of radio pager designs.
The PCD5003A is fully compatible with “CCIR Radio
paging Code No. 1” (also known as the POCSAG code)
operating at data rates of 512, 1200 and 2400 bits/s using
a single oscillator crystal of 76.8 kHz.
In addition to the standard POCSAG sync word the
PCD5003A is also capable of recognizing up to 4 User
Programmable Sync Words (UPSWs). This permits the
reception of both private services and POCSAG
transmissions via the same radio channel.
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5003A offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
Programmed Functions (SPFs), which eliminates the need
for external storage devices and interconnection. For other
non-volatile storage 20 bytes of general purpose
EEPROM are available. The low EEPROM programming
voltage makes the PCD5003A well suited for ‘over-the-air’
programming/reprogramming.
On request from an external controlling device or
automatically (by SPF programming), the PCD5003A will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
The PCD5003A can also produce a HIGH-level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
The PCD5003A contains a low-power, high-efficiency
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5003A.
Interface to such an external device is provided by an
I
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
1999 Jan 08
2
C-bus which allows received call identity and message
Enhanced Pager Decoder for POCSAG
FUNCTIONAL DESCRIPTION
Introduction
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between the devices. Pager status includes features
provided by the PCD5003A such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
A selectable low frequency timing reference is provided for
use in real-time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption.
Random and (optional) burst error correction techniques
are applied to the received data to optimize on call success
rate without increasing falsing rate beyond specified
POCSAG levels.
7.2
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each batch comprises 17 code-words of 32 bits each.
The first code-word is a synchronization code-word with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 code-words each, containing message
information. A code-word in a frame can either be an
address, message or idle code-word.
Idle code-words also have a fixed pattern and are used to
fill empty frames or to separate messages.
Address code-words are identified by an MSB of logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address code-word (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
Four different call types (‘numeric’, ‘alphanumeric’ and
two ‘alert only’ types) can be distinguished on each user
address. The call type is determined by two function bits in
the address code-word (bits 20 and 21), as shown in
Table 1.
The POCSAG paging code
Product specification
PCD5003A