PCD5003AH Philips Semiconductors, PCD5003AH Datasheet - Page 8

• Manufacturer Part Number: PCD5003AH
• Description: Enhanced Pager Decoder for POCSAG
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 1 POCSAG recommended call types and function bits
7.3
Table 2 Error correction
7.4
The PCD5003A has 2 operating states:
The operating state is determined by a Direct Control input
(DON) and bit D4 in the control register (see Table 3).
Table 3 Truth table for decoder operating status
7.5
In ON status the decoder pulses the receiver and oscillator
enable outputs (respectively RXE and ROE) according to
the code structure and the synchronization algorithm. Data
received serially at the data input (RDI) is processed for
call receipt. Reception of a valid paging call is signalled to
the microcontroller by means of an interrupt signal.
The received address and message data can then be read
via the I
1999 Jan 08
Preamble
Synchronization code-word
Address code-word
Message code-word
ON status
OFF status.
Enhanced Pager Decoder for POCSAG
DON INPUT
Error correction
Operating states
ON status
BIT 20 (MSB)
2
C-bus interface.
0
0
1
1
0
0
1
1
CONTROL
BIT D4
ITEM
0
1
0
1
BIT 21 (LSB)
OPERATING
STATUS
0
1
0
1
OFF
ON
ON
ON
4 random errors in 31 bits
2 random errors in 32 bits
2 random errors; plus 4-bit burst errors (optional)
2 random errors; plus 4-bit burst errors (optional)
8
7.6
In OFF status the decoder will neither activate the receiver
or oscillator enable outputs, nor process any data at the
data input. The crystal oscillator remains active to permit
communication with the microcontroller.
In both operating states an accurate timing reference is
available via the REF output. By SPF programming the
signal periodicity may be selected as 32.768 kHz, 50 Hz,
2 Hz or
7.7
The decoder can be reset by applying a positive pulse on
input pin RST. A power-on reset circuit consisting of an
RC network can be connected to this input as well.
Conditions during and after a reset are described in
Chapter “Operating instructions”.
For successful reset at power-on, a HIGH level must be
present on the RST pin while the device is powering-up.
This can be applied by the microcontroller, or via a suitable
RC power-on reset circuit connected to the RST input.
Reset circuit details and conditions during and after a reset
are described in Chapter 8.
alphanumeric
CALL TYPE
OFF status
Reset
alert only 1
alert only 2
1
numeric
60
Hz.
DESCRIPTION
7-bits per ASCII character
DATA FORMAT
4-bits per digit
Product specification
PCD5003A