MSP3421G MICRONAS [Micronas], MSP3421G Datasheet - Page 17

• Manufacturer Part Number: MSP3421G
• Description: Multistandard Sound Processor Family with Virtual Dolby Surround
• Manufacturer: MICRONAS [Micronas]

PRELIMINARY DATA SHEET
3. Control Interface
3.1. I
The MSP 34x1G is controlled via the I
interface.
The IC is selected by transmitting one of the
MSP 34x1G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x1G responds to different device addresses. A
device address pair is defined as a write address and a
read address (see Table 3–1).
Writing is done by sending the write device address,
followed by the subaddress byte, two address bytes,
and two data bytes.
Reading is done by sending the write device address,
followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device
read address and reading two bytes of data.
Refer to Section 3.1.3. for the I
Section 3.4. “Programming Tips” on page 45 for pro-
posals of MSP 34x1G I
for a list of available subaddresses.
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I
Due to the architecture of the MSP 34x1G, the IC can-
not react immediately to an I
Table 3–1: I
Table 3–2: I
Micronas
ADR_SEL
Mode
MSP device address
Name
CONTROL
WR_DEM
RD_DEM
WR_DSP
RD_DSP
2
C Bus Interface
2
2
C Bus Device Addresses
C Bus Subaddresses
Binary Value
0000 0000
0001 0000
0001 0001
0001 0010
0001 0011
2
C telegrams. See Table 3–2
Write
80
hex
2
(connected to DVSS)
C request. The typical
2
C bus protocol and to
2
C bus.
Low
Hex Value
00
10
11
12
13
2
C bus slave
Read
81
hex
Mode
Read/Write
Write
Write
Write
Write
Write
84
(connected to DVSUP)
hex
response time is about 0.3 ms. If the MSP cannot
accept another byte of data (e.g. while servicing an
internal interrupt), it holds the clock line I2C_CL low to
force the transmitter into a wait state. The I
Master must read back the clock line to detect when
the MSP is ready to receive the next I
The positions within a transmission where this may
happen are indicated by ’Wait’ in Section 3.1.3. The
maximum wait period of the MSP during normal opera-
tion mode is less than 1 ms.
3.1.1. Internal Hardware Error Handling
In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP’s wait period is
extended to 1.8 ms. After this time period elapses, the
MSP releases data and clock lines.
Indication and solving the error status:
To indicate the error status, the remaining acknowl-
edge bits of the actual I
Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I
the RESET condition to CONTROL.
Indication of reset:
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I
Fig. 4–27 on page 69.
High
Function
Write: Software reset of MSP (see Table 3–3)
Read: Hardware error status of MSP
write address demodulator
read address demodulator
write address DSP
read address DSP
Read
85
hex
2
C-protocol will be left high.
Write
88
hex
2
MSP 34x1G
C bus by transmitting
2
Left Open
C bus is shown in
2
C transmission.
Read
89
hex
2
C Bus
17