MSP3421G MICRONAS [Micronas], MSP3421G Datasheet - Page 19

• Manufacturer Part Number: MSP3421G
• Description: Multistandard Sound Processor Family with Virtual Dolby Surround
• Manufacturer: MICRONAS [Micronas]

PRELIMINARY DATA SHEET
Fig. 3–1: I
3.1.4. Proposals for General MSP 34x1G
3.1.4.1. Symbols
daw
dar
<
>
aa
dd
3.1.4.2. Write Telegrams
<daw 00 d0 00>
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
3.1.4.3. Read Telegrams
<daw 00 <dar dd dd>
<daw 11 aa aa <dar dd dd>
<daw 13 aa aa <dar dd dd>
3.1.4.4. Examples
<80 00 80 00>
<80 00 00 00>
<80 10 00 20 00 03>
<80 11 02 00 <81 dd dd>
<80 12 00 08 01 20>
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 45.
Micronas
I2C_DA
I2C_CL
I
2
C Telegrams
write device address (80
read device address (81
Start Condition
Stop Condition
Address Byte
Data Byte
2
C bus protocol (MSB first; data must be stable while clock is high)
S
write to CONTROL register
write data into demodulator
write data into DSP
RESET MSP statically
Clear RESET
Set demodulator to stand. 03
Read STATUS
Set loudspeaker channel
source to NICAM and
Matrix to STEREO
read data from
CONTROL register
read data from demodulator
read data from DSP
hex
hex
, 85
, 84
hex
hex
or 89
or 88
1
0
hex
hex
)
)
hex
3.2. Start-Up Sequence:
After POWER-ON or RESET (see Fig. 4–26), the IC is
in an inactive state. All registers are in the Reset posi-
tion (see Table 3–5 and Table 3–6), the analog outputs
are muted. The controller has to initialize all registers
for which a non-default setting is necessary.
3.3. MSP 34x1G Programming Interface
3.3.1. User Registers Overview
The MSP 34x1G is controlled by means of user regis-
ters. The complete list of all user registers is given in
Table 3–5 and Table 3–6. The registers are partitioned
into the Demodulator section (subaddress 10
writing, 11
ing sections (subaddress 12
reading).
Write and read registers are 16 bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I
to take place in 16-bit words (two byte transfers, with the
most significant byte transferred first). All write registers,
except the demodulator write registers are readable.
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
For
MSP 34xxD, a Manual/Compatibility Mode is available.
More read and write registers together with a detailed
description can be found in “Appendix B: Manual/Com-
patibility Mode” on page 85.
Power-Up and I
reasons
hex
for reading) and the Baseband Process-
P
of
2
software
C-Controlling
hex
compatibility
MSP 34x1G
for writing, 13
2
C bus have
to
hex
hex
the
for
for
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