MSP3421G MICRONAS [Micronas], MSP3421G Datasheet - Page 65

• Manufacturer Part Number: MSP3421G
• Description: Multistandard Sound Processor Family with Virtual Dolby Surround
• Manufacturer: MICRONAS [Micronas]

PRELIMINARY DATA SHEET
4.6.2.4. Crystal Recommendations
Micronas
Symbol
General Crystal Recommendations
f
R
C
C
Crystal Recommendations for Master-Slave Applications
f
D
C
f
Crystal Recommendations for FM / NICAM Applications
f
D
C
f
Crystal Recommendations for all analog FM/AM Applications
f
D
f
Amplitude Recommendation for Operation with External Clock Input (C
V
1)
P
TOL
CL
TOL
CL
TOL
CL
XCA
R
0
L
TEM
1
TEM
1
TEM
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-
quency of the internal PLL and to stabilize the frequency in closed-loop operation.
Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The sug-
gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.
To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the fre-
quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz
as closely as possible. The higher the capacity, the lower the resulting clock frequency.
Parameter
Crystal Parallel Resonance Fre-
quency at 12 pF Load Capacitance
Crystal Series Resistance
Crystal Shunt (Parallel) Capacitance
External Load Capacitance
Accuracy of Adjustment
Frequency Variation
versus Temperature
Motional (Dynamic) Capacitance
Required Open Loop Clock
Frequency (T
Accuracy of Adjustment
Frequency Variation
versus Temperature
Motional (Dynamic) Capacitance
Required Open Loop Clock
Frequency (T
Accuracy of Adjustment
Frequency Variation
versus Temperature
Required Open Loop Clock
Frequency (T
External Clock Amplitude
amb
amb
amb
= 25 C)
= 25 C)
= 25 C)
1)
Pin Name
XTAL_IN,
XTAL_OUT
AUD_CL_OUT
AUD_CL_OUT
AUD_CL_OUT
XTAL_IN
(No MSP-clock synchronization to I
(MSP-clock must perform synchronization to I
(No MSP-clock synchronization to I
Min.
PSDIP
P(L)QFP approx. 3.3
19
18.431
15
18.4305
18.429
0.7
load
20
20
30
30
100
50
after reset typ. 22 pF)
Typ.
18.432
8
6.2
approx. 1.5
24
MSP 34x1G
2
S clock possible)
Max.
25
7.0
18.433
18.4335
18.435
20
20
30
30
100
50
2
S clock possible)
2
S clock)
Unit
MHz
pF
pF
pF
ppm
ppm
fF
MHz
ppm
ppm
fF
MHz
ppm
ppm
MHz
V
pp
65