MSP3421G MICRONAS [Micronas], MSP3421G Datasheet - Page 26

• Manufacturer Part Number: MSP3421G
• Description: Multistandard Sound Processor Family with Virtual Dolby Surround
• Manufacturer: MICRONAS [Micronas]

MSP 34x1G
3.3.2.4. Write Registers on I
Table 3–9: Write Registers on I
26
Register
Address
00 20
00 30
1)
Valid at the next start of Automatic Standard Detection.
hex
hex
Function
STANDARD SELECTION Register
Defines TV Sound or FM-Radio Standard
bit[15:0]
MODUS Register
Preference in Automatic Standard Detection:
bit[15]
bit[14:13]
bit[12]
General MSP 34x1G Options
bit[11:9]
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
00 01
00 02
...
00 60
0
0
1
2
3
0
1
0
0/1
0/1
0
1
0/1
0/1
0
1
0
0/1
0/1
2
C Subaddress 10
2
hex
hex
hex
C Subaddress 10
start Automatic Standard Detection
Standard Codes (see Table 3–7)
undefined, must be 0
detected 4.5 MHz carrier is interpreted as:
standard M (Korea)
standard M (BTSC)
standard M (Japan)
chroma carrier (M/N standards are ignored)
detected 6.5 MHz carrier is interpreted as:
standard L (SECAM)
standard D/K1, D/K2, D/K3, or D/K NICAM
undefined, must be 0
ANA_IN1+/ANA_IN2+; select analog sound IF input pin
active/tristate state of audio clock output pin
AUD_CL_OUT
I
WS changes at data word boundary
WS changes one clock cycle in advance
master/slave mode of I
(= Master) in case of NICAM mode)
active/tristate state of I
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
undefined, must be 0
disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
off/on: Automatic Sound Select
2
S word strobe alignment
hex
hex
2
2
S output pins
S interface (must be set to 0
1)
1)
PRELIMINARY DATA SHEET
Name
STANDARD_SEL
MODUS
Micronas