PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 102

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-39. 32-bit Target Burst Read Transaction with a 32-bit Local Interface (Continued)
CLK
10
4
5
6
7
8
9
Turn around
PCI Data
Phase
Data 1
Data 2
Data 3
Wait
Wait
Idle
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on clock after bar_hit. If the
back-end will be ready to put data out on the next cycle, it can assert lt_rdyn.
The Core asserts lt_data_xfern since lt_rdyn was asserted the previous cycle. The back-
end drives the first DWORD (Data 1) on l_ad_in.
With lt_rdyn asserted for the previous two cycles, the burst cycle starts, so the Core asserts
trdyn and puts Data 1 on ad[31:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the target keeps
lt_data_xfern asserted to the back-end. The back-end can increment the address counter and
put the next DWORD (Data 2) on l_ad_in.
If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables (Byte Enable 2) on cben[3:0].
If the back-end keeps lt_rdyn asserted for the previous two cycles, the Core keeps trdyn
asserted and puts Data 2 on ad[31:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps lt_data_xfern
asserted to the back-end. The back-end can increment the address counter and put the next
DWORD (Data 3) on l_ad_in.
If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables (Byte Enable 3) on cben[3:0].
The master signals the end of the burst when it de-asserts framen.If the back-end keeps
lt_rdyn asserted previous two cycles, the Core keeps trdyn asserted and puts Data 3 on
ad[31:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps lt_data_xfern
asserted to the back-end application. The back-end can increment the address counter and put
the next DWORD (Don’t care) on l_ad_in.
The master relinquishes control of framen and cben[3:0]. It de-asserts irdyn if both trdyn
and irdyn were asserted last cycle.The Core relinquishes control of ad[31:0]. It de-asserts
both devseln and trdyn if both trdyn and irdyn were asserted last cycle. The Core also sig-
nals to the back-end that the transaction is complete by clearing bar_hit. The Core de-asserts
lt_data_xfern.
The Core relinquishes control of devseln and trdyn.
102
Description
Functional Description
PCI IP Core User’s Guide