PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 17

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-4. Local Interface Signals
Local Target Interface
lt_abortn
lt_disconnectn
lt_rdyn
lt_r_nw
lt_accessn
lt_data_xfern
Local Target Address Decode
bar_hit[5:0]
new_cap_hit
Local Master req/gnt
lm_req32n
lm_req64n
lm_gntn
Local Master Interface Control
lm_rdyn
lm_burst_length [11:0]
lm_data_xfern
lm_r_nw
lm_timeoutn
lm_abortn
Name
3
out
out
out
out
out
out
out
out
out
I/O
in
in
in
in
in
in
in
in
1
Polarity
(Continued)
high
high
low
low
low
low
low
low
low
low
low
low
—
—
—
—
—
Local target abort request is used to request a target abort on the PCI bus.
Local target disconnect (or retry) is used to request early termination of a
bus transaction on the PCI bus.
Local target ready signal indicates that the Local Interface is ready to
receive or send data.
Read/Write (read/not write) to signal whether the current transaction is a
read or write. 1 = read, 0 = write
Local target can access local interface if lt_accessn is active. Once
lt_accessn active, local target needs to be ready for next process based
on lt_command_out. lt_accessn is active during either of active
bar_hit, exprom_hit or new_cap_hit. It is also active during special
cycle command.
This signal indicates local input data (l_ad_in) being read or local output
data (l_data_out) being available at current clock cycle. When
lt_data_xfern is active, if core reads data from l_ad_in, back-end can
update l_ad_in for next data at next clock cycle. If core writes data on
l_data_out, back-end can get valid data from l_data_out. It is only
used when the local bus is 32 bits.
The bar_hit signal indicates that the master is requesting a transaction
that falls within one of the Base Address register ranges.
New Capabilities List hit. new_cap_hit indicates that the master is
requesting a Configuration Space register out of internal registers (00h-3fh),
that is 40h-FFh., Although the hardware associated with the New Capabili-
ties reside in the back-end logic, logically they are part of the PCI Configura-
tion Space.
Local master 32-bit data transaction request.
Local master 64-bit data transaction request.
Signal to the local master that gntn is asserted.
Local master is ready to receive data (read) or send data (write)
Local master burst length determines the number of data phases in the
transaction. For single data phase, it should be set to 1.
lm_burst_length set to 0 means the burst length is
13'b1,0000,0000,0000.
This signal indicates local input data (l_ad_in) being read or local output
data (l_data_out) available at current clock cycle. When
lt_data_xfern is active, if core reads data from l_ad_in, back-end can
update l_ad_in for next data at next clock cycle. If core writes data on
l_data_out, back-end can get valid data from l_data_out. It is only
used when the local bus is 32 bits. In a single data phase, it should be set to
1. lm_burst_length set by 0 means the length is 13'b1,0000,0000,0000.
(Read/Write) to signal whether the current transaction is a read or write. 
1 = read, 0 = write
Indicates that the transaction has timed out.
Local master issues an abort to terminate a cycle that can not be com-
pleted.
17
Description
Functional Description
PCI IP Core User’s Guide